Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2001-08-20
2003-02-18
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S220000
Reexamination Certificate
active
06522588
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for storing and outputting data, in which date are stored in a memory and in which a predetermined quantity of the data from the memory are loaded into a buffer memory. The data are subsequently output from the buffer memory through an output unit. A control unit is provided for controlling the data transfers and the associated components.
The publication titled“How to use Virtual Channel SDRAM”, User's Manual (M13311EJ1V0UM00), July 1998, from NEC, discloses SDRAM memories in which data of a segment from a memory bank are loaded into a memory channel. The segment is selected from a defined row of the memory bank. After buffer storage in the memory channel, the data are output via an interface via the specification of the column address. The use of the memory channel affords the possibility of buffer-storing data from a memory having a relatively long access time into a buffer memory having a short access time and subsequently outputting them. In this way, on statistical average the data can be read more rapidly from the memory. Since the data are read segment by segment into the memory channel, a relatively large interference signal is generated on account of the large number of data in the course of reading into the memory channel, with the result that the waiting time after which the data read during a read operation (in the sense amplifier, i.e. after a sensing operation) can be written to the memory channel is relatively long. This increases the total waiting time before the data can be output via the interface.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method and a device for storing and outputting data with a virtual channel which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which the data can be output more rapidly via an interface.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for storing and outputting data. The method includes storing the data in a memory, and loading a predetermined quantity of the data from the memory into a buffer memory. The loading step includes determining a predetermined number of selected data of the predetermined quantity that is intended to be output first, and loading the selected data into the buffer memory temporally before loading remaining data of the predetermined quantity. The selected data are output from the buffer memory through an output unit and then the remaining data are output from the buffer memory through the output unit.
It is advantageous for the data which are intended to be output first via the interface to be selected and written temporally first to the buffer memory and for the remaining data of the segment to be read into the buffer memory only at a later point in time. Since the data read in first constitute a very much smaller number than the data of the entire segment, the interference signal generated by the process of writing to the buffer memory is also significantly smaller, with the result that the data can be output from the buffer memory via the interface after a shorter waiting time.
In a further advantageous embodiment, the data, which are intended to be output first via the interface are selected and written to a predetermined area of the buffer memory. The remaining data of the segment are preferably also written simultaneously to another area of the buffer memory. Since the selected data constitute a smaller number, the interference signal generated by the selected data in the predetermined area of the buffer memory is also significantly smaller than the interference signal generated by the remaining data of the segment. As a result, the selected data can be output via the interface after a shorter waiting time than the remaining data of the segment.
Preferably, the number of data which can be output simultaneously via the interface are selected from the segment. Effective adaptation of the selected data to the output type of the interface is achieved in this way.
In accordance with an added mode of the invention, there is the step of configuring the memory as a semiconductor memory having memory cells for storing the data. The data stored in the memory cells are loaded into the buffer memory using an amplifying circuit.
In accordance with an additional mode of the invention, there is the step of outputting the data using a parallel interface with n lines and in that n data as the selected data are transferred temporally first into the buffer memory and subsequently output via the parallel interface.
In accordance with another mode of the invention, there is the step of writing the remaining data to the buffer memory temporally later than the predetermined number of the selected data.
With the foregoing and other objects in view there is provided, in accordance with the invention, a device for storing and reading out data. The device contains a memory, a buffer memory connected to the memory, an output unit connected to the buffer memory, and a control unit for defining a total quantity of the data intended to be read out and connected to the memory, the buffer memory and the output unit. The control unit determines a predetermined number of selected data that are intended to be read out first from the total quantity of the data. The control unit first initiates the loading of the selected data into the buffer memory and subsequently outputs the selected data using the output unit.
In accordance with an added feature of the invention, the control unit loads remaining data of the total quantity of the data into the buffer memory before the outputting of the selected data from the buffer memory and outputs the remaining data after the outputting of the selected data from the buffer memory.
In accordance with a further feature of the invention, the memory is a matrix-type semiconductor memory having memory cells. An amplifier circuit is connected to the memory cells and the buffer memory, and a column decoder and a row decoder are each connected to the memory cells and the control unit. The control unit addresses individually the memory cells by driving the column decoder and the row decoder and transfers the data of the memory cells through the amplifier circuit to the buffer memory.
In accordance with a concomitant feature of the invention, the memory buffer has memory rows. The output unit is an interface with n parallel data lines connected to the memory rows of the buffer memory, and the memory rows can be read out simultaneously from the buffer memory.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method and a device for storing and outputting data with a virtual channel, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 6064404 (2000-05-01), Aras et al.
patent: 6128244 (2000-10-01), Thompson et al.
patent: 6351423 (2002-02-01), Ooishi
patent: 199 32 683 (2000-02-01), None
Ho-Jun Song et al.: A 200 MHz Register-Based Wave-Pipelined 64M Synchronous DRAM, IEEE Journal of Solid-State Ciruits, vol. 32, No. 1, Jan. 1997, pp. 92-99.
Anonymous: “Virtual Channel SDRAM”,NEC User's Manual, Jul. 1998, No. M13311EJ1V0UM00, pp. 1-10.
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
Tran M.
LandOfFree
Method and device for storing and outputting data with a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and device for storing and outputting data with a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and device for storing and outputting data with a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3159188