Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1999-02-26
2002-06-04
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C709S216000, C709S238000, C709S245000, C370S351000, C370S474000
Reexamination Certificate
active
06401171
ABSTRACT:
TECHNICAL FIELD
The present invention relates to data communication networks wherein data messages are routed from node to node and particularly to a method and a device for storing an IP header in the cache memory of a data communication network node.
BACKGROUND OF THE INVENTION
One way to improve processing performance in a network node is to add a fast cache memory to the node to work jointly with the node's main memory.
When a node having a cache memory generates a request for data stored at a particular main memory address, the request is directed first to the cache memory. The cache memory controller checks to see if the requested data is already stored in the cache memory. If it is (a cache hit), the data is supplied from cache memory instead of main memory, which reduces the memory fetch time. If the cache memory does not include the requested data (a cache miss), the request is forwarded to main memory which returns the addressed data to the node's data processing logic. Where data must be retrieved from main memory, the the data and its associated address are written into the cache memory during the retrieval step so that future requests for the data may be filled from cache memory, rather than main memory.
A node in a data communication network that handles Internet Protocol (IP) data traffic generally includes a cache memory associated with the main memory. When a message is received by the node, the following steps are conventionally performed:
1. The whole message, comprising an IP header and the data, is stored in the main memory.
2. Assuming the IP header is not already stored in cache memory, the node processor reads the IP header from the main memory and computes the IP routing algorithm. The cache memory controller uses this memory access to write the IP header into a cache memory cell.
3. Then the node processor writes the new IP header to the main memory and the cache memory updates the matching cache memory cell.
4. Finally, the complete message, that is, data retrieved from main memory and the related IP header retrieved from the cache memory is sent over the network.
SUMMARY OF THE INVENTION
An object of the invention is to provide a method and a device for writing an IP if header in a received message into cache memory of a network node concurrently with the first main memory write operation.
The invention relates to a method of storing a message header such as a IP header in a cache memory, this method being implemented in a data transmission network having a plurality of nodes wherein messages including a header and data are routed from node to node along a transmission route and wherein each node includes processing means for computing a routing algorithm by using the header of a message received by the node and routing the message to another node by using the resulting information, a main memory for storing the message and a cache memory. Such a method comprises the steps of storing the header in the cache memory while it is being stored in the main memory, reading the header from the cache memory in order to compute the routing algorithm, writing a new header resulting from the routing algorithm into the cache memory, and reading the new header from the cache memory and the message data stored in the main memory to enable the routing of a message including the header and the message data over the network.
According to another aspect, the invention relates to a device for storing in a cache memory of a node the IP header of a message routed from node to node in a data transmission network wherein each node includes a processor for computing a routing algorithm by using the header and routing the message by using the resulting information, a main memory for storing the message, a cache memory; and header a detector logic for checking whether the message conforms to a predetermined protocol such as IP protocol and cache control logic for storing the header in the cache memory concurrently with its storage in the main memory.
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Dispensa Jean-Claude
Jay Alexandre
Klein Philippe
Loison Jean-Philippe
Cesari and McKenna LLP
Cisco Technology Inc.
Johnston A. Sidney
Kim Matthew
Vital Pierre M.
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