Method and device for reducing interface area of a memory...

Details Method and device for reducing interface area of a memory... Method and device for reducing interface area of a memory...

2006-12-19

2006-12-19

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S238000, C438S381000, C257SE21008, C257S613000, C257S694000, C257S645000

Reexamination Certificate

active

07151027

ABSTRACT:
A method and device for reducing interface area of a memory device. A poly-2 layer is formed above a substrate at an interface between a memory array and a periphery of the memory device. The poly-2 layer is etched proximate to the memory array. The poly-2 layer is etched proximate to the periphery such that a portion of the poly-2 layer remains at the interface.

REFERENCES:
patent: 5303185 (1994-04-01), Hazani
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patent: 5953254 (1999-09-01), Pourkeramati
patent: 6037222 (2000-03-01), Huang et al.
patent: 6808985 (2004-10-01), Lee et al.
patent: 2005/0127428 (2005-06-01), Mokhlesi et al.

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