Method and device for reading and for checking the time...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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C365S201000

Reexamination Certificate

active

06871306

ABSTRACT:
A method and a device for reading and for checking the time position of a data response read out from a memory module to be tested, in particular a DRAM memory operating in DDR operation. In a test receiver, the data response from the memory module to be tested is latched into a data latch with a data strobe response signal that has been delayed. A symmetrical clock signal is generated as a calibration signal. The calibration signal is used to calibrate the time position of the delayed data strobe response signal with respect to the data response. The delayed data strobe response signal is used for latching the data response. The delay time is programmed into a delay device during the calibration operation and also supplies a measure for testing precise time relationships between the data strobe response signal (DQS) and the data response.

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patent: 6671836 (2003-12-01), Lai et al.
patent: 6721904 (2004-04-01), Ernst et al.
patent: 20030191995 (2003-10-01), Abrosimov et al.

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