Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
Reexamination Certificate
1997-12-19
2001-08-21
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Specialized instruction processing in support of testing,...
C714S030000, C714S045000, C714S046000, C714S727000
Reexamination Certificate
active
06279103
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to providing an instruction trace. In particular, it relates to a single chip integrated circuit device on which an instruction trace is collected, and to a method of providing an instruction trace.
BACKGROUND TO THE INVENTION
CPUs contain in addition to their fetch and execute circuitry for fetching and executing instructions from a memory, an instruction pointer register which holds the address in memory of an instruction to be executed by the CPU. Knowledge of the address held in the instruction pointer register is of particular importance when performing diagnostic functions on software which is running on a CPU. In some, simple, cases, the address held as the instruction pointer can be deduced by observing the memory address value on an external memory bus. However, in many cases the instruction pointer is hidden within the depths of the CPU and is not readily accessible outside the CPU.
In particular, in the past CPUs were manufactured as a single chip, requiring off-chip access to all their ancillary circuitry, such as memory. As a result, they had a plurality of access pins so that information about the CPU, in particular memory address information, was in any event externally available from these access pins.
Nowadays, chips are more complex and contain not only a processor on-chip but also its associated memory and other ancillary circuitry. It is no longer a simple matter to monitor the operation of the processor because the signals which are normally available off-chip no longer provide a direct indication as to the internal operation of the CPU.
With the increasing complexity of software designed to run on integrated CPUs, it is increasingly important to adequately test the software. This requires techniques for monitoring operation of the CPU while it executes the software. It is a particularly onerous requirement that the software be monitored non-intrusively while it is operating in real time.
So-called diagnostic or debugging techniques have been developed in an attempt: to achieve this. One of these techniques is to use a logic state analyser (LSA). This is a device connected to the pins of the integrated circuit which monitors continuously the state of all off-chip communications. Each sequentially produced set of states is stored and can then be analysed. Not only is an LSA expensive, but it requires a large amount of deduction and analysis to derive any useful information from the huge number of sequentially produced state sets which are stored. As it is only possible to analyse the status signals being communicated off-chip, it is inevitably necessary to make some deduction or hypothesis concerning the on-chip situation. It is sometimes possible by this technique to deduce instruction pointers. The sequence of addresses stored in the instruction pointer register which is captured by the LSA is referred to as an instruction trace.
Sometimes it is also possible to create an instruction trace in an equivalent virtual environment by software simulation, hardware simulation, hardware emulation or other means. However, none of these techniques reflect the real world situation or real time sequence of events. Such a trace is often useful for comparing against a real time instruction trace, but is otherwise of limited value in diagnostic procedures.
In any event, none of these techniques can be used to find out information concerning the instruction pointer unless it can be deduced by observing external connection pins. If there are no existing external connection pins, external connection pins may sometimes be added specifically to retrieve the instruction pointer from the instruction pointer register. This is an additional overhead to the chip solely for the purpose of debugging. Moreover, in some circumstances even this is not possible.
SUMMARY OF THE INVENTION
According to the present invention there is provided a single chip integrated circuit device comprising:
an on-chip CPU comprising fetch and execute circuitry for fetching and executing instructions from a memory, and an instruction pointer register for holding sequentially addresses in memory of instructions to be executed by the CPU;
an instruction trace controller operable to monitor said addresses and being connected to trace storage locations for causing selected ones of said addresses to be stored at said trace locations, dependent on detection that one of said addresses is not the next sequential address in memory after the previous one of said addresses.
Thus, an on-chip instruction trace controller allows an instruction trace to be collected, in real time, without the need for additional external connection pins. By only storing the value of the instruction pointer at discontinuities (non-sequential addresses), the amount of information which needs to be stored over a given period of time is considerably reduced.
The instruction trace controller can be connected to the instruction pointer register for monitoring said addresses. Alternatively, it can be connected to a memory bus along which instructions are fetched to the CPU to monitor said addresses.
The trace storage locations can be provided in a dedicated memory connected to the trace controller by a dedicated bus, in a dedicated memory connected to a memory bus which also allows accesses from the CPU, or in the same memory as that which is accessible by the CPU, either on or off-chip. Where the memory is off-chip, it can be connected to the on-chip bus by an external memory interface controller. Alternatively, it can be associated with a host CPU which is connected to the chip by an off-chip serial communications link.
The non-sequential addresses or discontinuities can either be detected by the instruction trace controller itself or can be identified when the instruction pointer is sent from the CPU to the instruction trace controller.
Where access to memory is slow to permit the trace addresses to be stored, the instruction trace controller can be operable to stall the normal operation of the CPU to allow said addresses to be stored at said trace storage locations.
The instruction trace controller can comprise one or more of the following registers:
a destination address register which holds the address of the next trace storage location where the next selected address is to be stored;
a first register for storing one of said addresses immediately prior to detection of a discontinuity;
a second register for storing one of said addresses immediately following detection of a discontinuity;
a size register for setting the size of a dedicated memory or trace buffer for the instruction trace controller; and
an option control bit register for selecting one or more options to be implemented by the instruction trace controller.
The option control bits register can control whether or not the first register is used or the second register is used or both. The option control register can also determine whether or not a stall CPU signal is to be sent when the trace storage locations are not readily available. The option control bits register can also interrupt the CPU when the trace storage locations become full (i.e. when the trace storage locations reach their size limit), or control the trace storage locations to roll over when they become full, or to control other selectable options.
According to another aspect of the present invention there is provided a method of providing an instruction trace from an on-chip CPU within a single chip integrated circuit device, wherein addresses in memory of instructions to be executed by the CPU are held sequentially in an instruction pointer register of the CPU, said addresses being monitored by an instruction trace controller on the single chip integrated circuit device which instruction trace controller is operable to cause selected ones of said addresses to be stored at predetermined trace storage locations dependent on detection that one of said addresses is not the next sequential address in memory after the previous one of said addresses.
REFERENCES
Chan Eddie
Galanthay Theodore E.
Morris James H.
Patel Gautam R.
SGS-Thomson Microelectronics Limited
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