Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Patent
1997-02-28
2000-11-28
Peikari, B. James
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
711204, 711167, 711169, G06F 926
Patent
active
06154826&
ABSTRACT:
A data processing system is disclosed which comprises a data processor and memory control device for controlling the access of information from the memory. The memory control device includes temporary storage and decision ability for determining what order to execute the memory accesses. The compiler detects the requirements of the data processor and selects the data to stream to the memory control device which determines a memory access order. The order in which to access said information is selected based on the location of information stored in the memory. The information is repeatedly accessed from memory and stored in the temporary storage until all streamed information is accessed. The information is stored until required by the data processor. The selection of the order in which to access information maximizes bandwidth and decreases the retrieval time.
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patent: 5313636 (1994-05-01), Noble et al.
patent: 5606207 (1997-02-01), Tomassi et al.
Tanenbaum, Structured Computer Organization, Second Edition, 1984, pp. 10-12.
Aylor James
Hitchcock Charles Young
Klenke Robert
McKee Sally A.
Moyer Stephen A.
Peikari B. James
University of Virginia Patent Foundation
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