Method and device employing polysilicon scaling

Details Method and device employing polysilicon scaling Method and device employing polysilicon scaling

2009-02-13

2011-12-13

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21683

Reexamination Certificate

active

08076199

ABSTRACT:
A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.

REFERENCES:
patent: 6436778 (2002-08-01), Fang et al.
patent: 7029976 (2006-04-01), Nagarad et al.
patent: 7217610 (2007-05-01), Graf et al.

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