Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-07-01
2004-08-17
Auduong, Gene N. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S154000
Reexamination Certificate
active
06778449
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to systems and methods of detecting electrical leakage current from an array of semiconductor devices and more particularly to a system and method that improves the ability to measure components of leakage current.
2. Description of the Related Art
Static random access memory (SRAM) is a commonly used memory device. When the power source supplied to SRAM is shut down, the data stored in SRAM disappears. The memory cells in SRAM are used to store data by changing the conduction state of the internal transistors in a memory cell. Once the data is written into the SRAM cell, the internal latch maintains the data state as long as power is supplied to the array. This is quite different from dynamic RAM (DRAM) which stores data by charging and discharging capacitors and must be frequently refreshed. Because SRAM does not require refresh and the read and write speed of SRAM is very fast so it is widely applied to computer systems.
With component arrays, such as memory arrays (SRAM arrays), the issue of standby power consumption is especially important for battery driven applications. An important factor of power consumption with large SRAM arrays is leakage current. Therefore, it is important to test memory arrays for leakage to evaluate whether a new design reduces leakage, as well as to determine whether the array was manufactured properly (without defects).
Conventional systems that test for current leakage do not allow sufficient flexibility for leakage component learning and often do not allow one to fully understand the leakage component of the full SRAM array and cell contribution. There is a need to increase the accuracy and flexibility of the current leakage detection methods. The invention described below provides systems/methods that dramatically increase the ability to detect and characterize the leakage current from memory arrays.
BRIEF SUMMARY OF THE INVENTION
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional current/voltage leakage detection systems the present invention has been devised, and it is an object of the present invention to provide a structure and method for an improved current/voltage leakage detection system.
In order to attain the object(s) suggested above, there is provided, according to one aspect of the invention, a test structure that has an array of cells connected together by conductive lines. The conductive lines connect the cells together as if they were a single cell. The conductive lines can include a common word line, a common bit line, a common bit line complement line, a common N-well voltage line, a common interior ground line, a common interior voltage line, and/or a common ground line.
Each of the conductive lines can include an individual test pad. By connecting to each test pad, the array can be tested for current leakage as if the array were an individual cell. Each word line contact pad is connected to the common word line. A bit line contact pad is connected to the common bit line. The invention also has a bit line complement contact pad that is connected to a common bit line complement line. A voltage contact pad is connected to a N-well voltage line. An interior ground contact pad is connected to a common interior ground line. An interior voltage contact pad is connected to the common interior voltage line and a ground line contact pad is connected to a common ground line.
The conductive lines join all word lines within the array as a single word line. The invention joins all bit lines within the array as a single bitline. The invention joins all voltage lines within the array as a single voltage line and also joins all ground lines together within the array as a single ground line.
The invention applies a voltage level to one conductive line to charge all the elements connected to that conductive line. The invention measures the current on one conductive line to determine the average value for all the elements connected to that conductive line.
The invention also tests an array structure by using conductive lines to connect cells within the array. First, the invention joins all word lines within the array as a single word line. Next, the invention joins all true and complement bit lines within the array as either a single true or complement bitline. The invention joins all voltage lines within the array as a single voltage line and then joins all ground lines together within the array as a single ground line. The invention then places an applied voltage on one or more of the conductive lines and measures the current leakage on the other conductive lines. The invention joins the voltage lines and joins all N-wells to a single voltage line. The invention joins all interior voltages of the cells to a single interior voltage line. The joining of the ground lines includes forming a connection to a substrate of the array and joining all interior grounds of the cells to a single interior ground line. The invention applies a voltage to one conductive line to charge all elements connected to the conductive line. The invention then measures the current on the conductive line to measure a leakage at a given applied voltage on all elements connected to that conductive line.
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Breitwisch Matthew J.
Brown Jeffrey S.
Mann Randy W.
Oppold Jeffrey H.
Auduong Gene N.
Chadurjian, Esq. Mark F.
International Business Machines - Corporation
McGinn & Gibb PLLC
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