Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-07-27
2001-06-05
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S194000, C365S233100, C365S189050, C365S191000
Reexamination Certificate
active
06243303
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to write control circuits generally and, more particularly, to a circuit and method for writing data that may be insensitive to input glitches.
BACKGROUND OF THE INVENTION
Conventional data transition detect (DTD) circuits can terminate a bit line write signal after a constant delay. Such circuits can operate on a single transition of a data input and can allow write recovery to start without waiting until the end of an active write cycle. Provided that the user meets tSD (e.g., data setup to end-of-write), the correct data is written. A change in data input must start a new write pulse, regardless of when that change occurs.
Address transition detect (ATD) circuits can operate on external data pins to generate a global write pulse signal.
Another approach may be found in U.S. Pat. No. 5,751,644, entitled Data Transition Detect Write Control, is illustrated in FIG.
1
and is hereby incorporated by reference in its entirety. The latch R/S
1
keeps the write driver (e.g., ND
3
and ND
4
) enabled for writing either a data 0 or a data 1. When the signal WR_
1
is equal to 1 and the signal WR_
0
is equal to 0, the circuit is enabled for writing a 1. When the signal WR_
1
is equal to 0 and the signal WR_
0
is equal to 1, the circuit is enabled for writing a 0. For example, when writing 1, the write driver is initially enabled for writing a 1. The data makes a 0 to 1 transition and the signal WDATAB switches from 1 to 0. The data 1 is written into the memory array. The delayed 1 to 0 transition (e.g., the wdata delay) switches the latch R/S
1
to be enabled for writing a 0 to end the write.
The main disadvantage of the circuit of
FIG. 1
is that it may be vulnerable to data input DIN glitches that may lead to write failure in the memory cell. If the data first makes a transition from 0 to 1, and then from 1 to 0, the pulse width at data input DIN may be such that data is written into the memory cell, but cannot change the state of the latch R/S
1
due to the filtering of the signal WDATA in the delay element. During such a condition, the write driver cannot write the new data 0, since it is still enabled for writing a 1. The same reasoning holds for the opposite data polarity.
The potential glitch condition may arise because the gates ND
3
and ND
4
are controlled by the two outputs of the same latch R/S
1
. There is no mechanism to keep the write driver enabled for either data polarity in the event of glitches or short pulses on data input signal DIN.
SUMMARY OF THE INVENTION
The present invention concerns a method of generating write control signals insensitive to glitches on a data input signal comprising the steps of (A) enabling a write of a first or second value in response to a data input transition, (B) holding in a ready state until the data input is stable and (C) writing stable data into a memory array.
The objects, features and advantages of the present invention include providing a circuit and method for writing data to a memory that may (i) be insensitive to data input glitches, (ii) provide independent latches for write driver control and/or (iii) operate in either polarity.
REFERENCES:
patent: 5305268 (1994-04-01), McClure
patent: 5384745 (1995-01-01), Konishi et al.
patent: 5404327 (1995-04-01), Houston
patent: 5631871 (1997-05-01), Park et al.
patent: 5717654 (1998-02-01), Manning
patent: 5721859 (1998-02-01), Manning
patent: 5751644 (1998-05-01), Ansel et al.
patent: 5764591 (1998-06-01), Matsui
patent: 6101134 (2000-08-01), Sacheti et al.
patent: 6101145 (2000-08-01), Nicholes
patent: 404339267 (1992-11-01), None
Ansel George M.
Baker William G.
Kelly James E.
Sancheti Sanjay K.
Christopher P. Maiorana P.C.
Cypress Semiconductor Corp.
Nguyen Viet Q.
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