Method and circuitry for preconditioning shorted rows in a nonvo

Details Method and circuitry for preconditioning shorted rows in a nonvo Method and circuitry for preconditioning shorted rows in a nonvo

1992-04-21

1994-09-13

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Precharge

365210, 365900, 365200, 36523006, 365218, 371 103, G11C 1140

Patent

active

053474899

ABSTRACT:
A method of preconditioning and verifying the preconditioning of memory cells within shorted rows of a memory array is described. Preconditioning begins by applying a preconditioning pulse to two memory cells that are shorted together. Afterward, one of the two shorted cells is read by applying a nominal gate voltage level to the gates of both of the shorted memory cells. At the same time, a shorted reference cell is read by applying a voltage level to its gate which less than the nominal gate voltage level. While the read voltages are being applied to the array cells and the shorted reference cell, the threshold voltage of one of the two shorted array cells is compared to the threshold voltage of the shorted reference cell. The shorted reference cell has a threshold voltage level that is lower than the level normally required for preconditioning but which is sufficient to prevent the quick overerasure of the shorted memory cells.

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patent: 5233559 (1993-08-01), Brennan, Jr.
patent: 5237535 (1993-08-01), Mielke et al.

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