Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-09-26
2003-03-25
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S158000, C365S207000, C365S210130
Reexamination Certificate
active
06538940
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor circuits, and more specifically, to semiconductor memory circuits.
BACKGROUND OF THE INVENTION
A form of semiconductor memory that has at least two distinct resistance states is the magnetoresistive random access memory (hereinafter referred to as “MRAM”). A key factor in the reading of an MRAM cell is the resistance of the tunnel junction in the MRAM cell. With a large number of cells in a memory array, there will be a distribution of resistance values due to manufacturing processing variations. If the resistance of the tunnel junction is too high, a bit in the low resistance state will look like it is in the high resistance state. On the other hand, if the resistance of the tunnel junction is too low, a bit in the high resistance state will look like it is in the low resistance state. If such an error occurs consistently, ordinary testing of the memory will detect the problem. However, if the resistance value of a bit is borderline, then the bit, referred to as a weak bit, will sometimes be correctly read and sometimes incorrectly read due to noise during the testing. This variation can lead to a problem with memories that pass during production testing but that erratically fail when in use in a system.
Numerous testing methodologies have been previously proposed for DRAMs, SRAMs and Flash memories as the existence of weak bits is well documented in the memory literature. U.S. Pat. No. 4,468,759 entitled “Testing Method and Apparatus for DRAM” by Roger Kung et al. is an example of a test methodology for a DRAM. Kung discloses the adjustment of a stored voltage on a dummy DRAM cell that is used as a read reference for detecting weak bits. The voltage is raised for ones and lowered for zeroes. MRAMs, in contrast, store a magnetic state rather than a voltage. U.S. Pat. No. 5,537,358 by Fong entitled “Flash Memory having Adaptive Memory and Method” uses voltage variations on reference bits to compensate for weak bits. U.S. Pat. No. 6,105,152 entitled “Devices and Method for Testing Cell Margin of Memory Devices” by Kevin Duesman et al. is another example of a memory test methodology for identifying weak bits. In this example, during the testing, at least one of the start time, duration, or voltage levels of the timing signals is varied to be outside of specified ranges which results in borderline memory cells failing. This technique does not directly control or disclose by at what point a weak bit failure occurs.
REFERENCES:
patent: 4468759 (1984-08-01), Kung et al.
patent: 5321842 (1994-06-01), Fairfield et al.
patent: 5537358 (1996-07-01), Fong
patent: 6105152 (2000-08-01), Duesman et al.
patent: 6128239 (2000-10-01), Perner
patent: 6385111 (2002-05-01), Tran et al.
patent: 6456524 (2002-09-01), Perner et al.
Andre Thomas W.
Garni Bradley J.
Nahas Joseph J.
Chiu Joanna G.
Dinh Son T.
King Robert L.
Motorola Inc.
LandOfFree
Method and circuitry for identifying weak bits in an MRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and circuitry for identifying weak bits in an MRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and circuitry for identifying weak bits in an MRAM will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3001210