Method and circuitry for enabling internal test operations in a

Details Method and circuitry for enabling internal test operations in a Method and circuitry for enabling internal test operations in a

1989-06-12

1990-04-17

Karlsen, Ernest F.

Static information storage and retrieval

Read/write circuit

Testing

371 212, 371 224, 371 225, G01R 3128

Patent

active

049183788

ABSTRACT:
A method for internal self-testing is provided for a VLSI chip having gates, logic, registers, memory circuitry, etc. The registers are connected into a shift chain circuit form. A set of control flip-flops operate to convert the registers to multifunction shift registers (MFSR's) which operate as flip-flops during a test cycle and as latches during normal operations. Selected MFSR's function to generate test patterns to the chip circuitry which have output signals to an output MFSR which collects a signature that can be compared to a predetermined signature to determine error-free or error-incurred operation of the VLSI circuitry.

REFERENCES:
patent: 4701920 (1987-10-01), Resnick et al.
patent: 4764926 (1988-08-01), Knight et al.
patent: 4768196 (1988-08-01), Jou et al.
patent: 4827476 (1989-05-01), Garcia

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