Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2007-08-21
2007-08-21
Cao, Chun (Department: 2115)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C710S060000
Reexamination Certificate
active
10480736
ABSTRACT:
In order to carry out an equidistant data transfer between clock domains having different clock rates, a combination of a counter (1) and a finite state machine (2) is proposed. Said counter (1) continuously counts off the clock cycles of the faster clock (CLK2, while the finite state machine (2) monitors the clock edges of the slower clock (CLK1) and an enabling signal (EN) for the data transfer with the faster clock (CLK2) is produced according to the count of the counter (1).
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Labate Francesco
Staber Michael
Cao Chun
Tran Vincent
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