Static information storage and retrieval – Read/write circuit – Testing
Patent
1998-03-30
1999-08-03
Mai, Son
Static information storage and retrieval
Read/write circuit
Testing
365233, G11C 700
Patent
active
059333790
ABSTRACT:
A circuit for testing a semiconductor memory device comprises a latency controller for controlling the latency of the external clock signal, an internal column address generator for generating a column address signal in the memory device, and a mode register for generating a mode signal. The circuit for testing semiconductor memory devices also includes a column address decoder for decoding the output address signal of the internal column address generator, a memory cell for reading or writing data, an input/output control unit for controlling the data input/output of the memory cell according to the output signal of the latency controller, a data input buffer, and a data output buffer. Further provided are a frequency multiplier for generating an internal clock signal having a frequency "n" times the frequency of the external clock signal. By providing the above-mentioned improvements, the conventional test equipment can be used to test high frequency memory devices.
REFERENCES:
patent: 5570381 (1996-10-01), Schofield
patent: 5757705 (1998-05-01), Manning
patent: 5805611 (1998-09-01), McClure
Cho Soo-In
Park Churoo
Mai Son
Samsung Electronics Co,. Ltd.
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