Method and circuit for synchronizing a higher frequency...

Details Method and circuit for synchronizing a higher frequency... Method and circuit for synchronizing a higher frequency...

2006-05-16

2006-05-16

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S500000, C713S501000, C713S502000

Reexamination Certificate

active

07047433

ABSTRACT:
A higher frequency clock and a lower frequency clock are locked at a predetermined phase relationship. A total number of pulses of the higher frequency clock occurring between two sequential rising edges of the lower frequency are calculated. A count start signal is generated in response to a rising edge of the lower frequency clock. A value of a lower frequency clock count is set in response to the count start signal. The value of the lower frequency clock decrements in accordance with a frequency of the higher frequency clock. When the value of the lower frequency clock has decreased by the total number of pulses of the higher frequency clock occurring between two consecutive rising edges of the lower frequency minus 1, a synchronization signal is generated for indicating occurrence of the predetermined phase relationship between the higher frequency clock and the lower frequency clock.

REFERENCES:
patent: 5459855 (1995-10-01), Lelm
patent: 6396887 (2002-05-01), Ware et al.
patent: 6711696 (2004-03-01), Bates et al.
patent: 6784716 (2004-08-01), Meguro

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