Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1995-04-11
1996-08-20
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
3652257, 36523003, G11C 700
Patent
active
055485553
ABSTRACT:
A method and a circuit for repairing defect by substituting a redundant memory cell for a defective memory cell in the semiconductor memory device. The circuit comprises charging nodes connected parallel to a number of electrical fuses; a device for outputting a storage signal of a defective address in response to an external control signal; a device for providing current to the charging node in response to the storage signal of the defective address; a redundant sense amplifier for outputting a redundant block driving signal to substitute a defective address in response to a logic level of the charging node; and a controller for decoding an address signal provided from the outside of the memory device so that a current path is formed in a selected fuse and the fuse is blew by current provided from the charging node, the controller being activated by the storage signal of the defective address.
REFERENCES:
patent: 4473895 (1984-09-01), Tatematsu
patent: 5297085 (1994-03-01), Choi et al.
patent: 5379259 (1995-01-01), Fujita
patent: 5392246 (1995-02-01), Akiyama et al.
patent: 5422850 (1995-06-01), Sukegawa et al.
Kim Jin-Ki
Lee Sung-Soo
Popek Joseph A.
Samsung Electronics Co,. Ltd.
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