Method and circuit for rearranging output data in variable-lengt

Details Method and circuit for rearranging output data in variable-lengt Method and circuit for rearranging output data in variable-lengt

1995-12-29

1998-10-13

Harvey, Jack B.

Television

Special applications

Simulator

348461, G06F 1300

Patent

active

058225528

ABSTRACT:
The invention relates to a method and a circuit for rearranging output data of a variable-length decoder (VLD). The circuit for rearranging output data of a VLD has an internal memory, a first data processor for packing a variable-length decoded bit stream in a data unit having a predetermined number or bits, generating a write address for each packed data unit to store the packed data unit in the internal memory, and generating a request signal for transmitting the stored packed data unit to an external memory, when the number of packed data units stored in the internal memory exceeds a predetermined threshold value, and a second data processor for generating respective read addresses for reading out N packed data units from the internal memory, when an accept signal is generated in response to the request signal, and applying the generated read address to the internal memory, wherein the N packed data units stored in the corresponding read address are sequentially read out from the internal memory and are transmitted to the external memory. Therefore, timing margins can be ensured through request and acceptance, and an automatic byte-alignment by start code is possible. Further, memory writing and reading timing is stabilized, and write and read banks of the memory are efficiently switched during writing and reading operations.

REFERENCES:
patent: 5426462 (1995-06-01), Bui
patent: 5502493 (1996-03-01), Meyer
patent: 5515106 (1996-05-01), Chaney et al.
patent: 5557271 (1996-09-01), Rim et al.
patent: 5579052 (1996-11-01), Artieri
patent: 5592399 (1997-01-01), Keith et al.

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