Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-10-10
2001-12-04
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S203000, C365S238500
Reexamination Certificate
active
06327192
ABSTRACT:
TECHNICAL FIELD
The present invention is directed generally to semiconductor memory devices and, more specifically, to a dynamic random access memory having hidden row access and row precharge times.
BACKGROUND OF THE INVENTION
Semiconductor memories are utilized in a variety of applications, including digital communications systems in which the memories may be used for the temporary storage of data transmitted to or received from a communications network. Communications networks increasingly transfer data at faster rates, so the semiconductor memories transferring data to or receiving data from the communications network must be capable of performing such transfers at corresponding faster rates. For example, some local and wide area communications networks may transfer data at a rate of up to 155 million bits per second (“Mbps”) in asynchronous transfer mode (“ATM”). Where such high data transfer rates are required, static random access memories (“SRAMs”) are typically utilized due to the relatively high bandwidth of SRAMs. The bandwidth of a memory device is the rate, in bits per second, at which data is transferred to and from the device. Although SRAMs provide the necessary bandwidth in such applications, they are relatively costly in terms of price per bit when compared to conventional dynamic random access memories (“DRAMs”). Thus, it is desirable to utilize DRAMs in place of SRAMs in these high-speed communications networks. Conventional DRAMs, however, have insufficient bandwidth to transfer data at the rates required by these high-speed communications networks.
FIG. 1
is a signal timing diagram of a read data transfer operation for a conventional DRAM having an address bus ADDR, a data bus DQ, and a control bus. As known in the art, the DRAM includes a memory-cell array comprising a number of memory cells arranged in rows and columns, each memory-cell storing a binary bit of data. To begin the read data transfer operation, an external circuit, such as a microprocessor or a DRAM controller, drives a write enable signal {overscore (WE)} high to define a read data transfer operation and drives an output enable signal {overscore (OE)} low to enable the DRAM to place addressed data on the data bus DQ. The external circuit then applies a row address ROWX on the address bus ADDR and drives a row address strobe signal {overscore (RAS)} low at a time t
0
. In response to the row address strobe signal {overscore (RAS)} going low, the DRAM latches the row address ROWX and row address decode circuitry decodes the row address ROWX and activates a corresponding row of memory cells in the memory-cell array. After the external circuit drives the row address strobe signal {overscore (RAS)} low, it delays for a fixed amount of time, places a column address COLM on the address bus ADDR, and thereafter drives a column address strobe signal {overscore (CAS)} low at a time t
1
. The DRAM latches the column address COLM in response to the signal {overscore (CAS)} going low and column address decode circuitry begins decoding the column address COLM. At about a time t
2
, the row address ROWX and column address COLM have been decoded and the DRAM places on the data bus DQ the addressed data D
1
where it is read by the external circuit.
After the external circuit has read the data D
1
, it drives the signals {overscore (OE)}, {overscore (RAS)}, and {overscore (CAS)} high in preparation for the next data transfer operation with the DRAM. In response to the signal {overscore (OE)} going high, the DRAM, after a short delay, removes the data D
1
from the data bus DQ. The external circuit must maintain the row address strobe signal {overscore (RAS)} high for at least a row precharge time t
RP
before beginning the next data transfer operation with the DRAM. The row precharge time t
RP
is the time required by the DRAM to precharge and equilibrate the memory-cell array and reset the address decode circuitry in anticipation of the next data transfer operation. In
FIG. 1
, the row precharge time t
RP
lasts from the time t
2
until a time t
3
at which time the external circuit begins the next read data transfer operation by placing a new row address ROWY on the data bus DQ and driving the row address strobe signal {overscore (RAS)} low causing the DRAM to latch and begin decoding the new row address ROWY. The external circuitry then places a new column address COLN on the address bus ADDR, drives the column address strobe signal {overscore (CAS)} low, and the DRAM, in response to the signal {overscore (CAS)} going low, latches and begins decoding the new column address COLN. The DRAM operates as previously described to supply new data D
2
on the data bus DQ where it is once again read by the external circuit.
The bandwidth of a conventional DRAM is limited by a cycle time t
RC
corresponding to the minimum amount of time the external circuit must wait between consecutive data transfer operations. This is true because data can be read from the DRAM only once during the cycle time t
RC
.The cycle time t
RC
is approximately equal to the sum of the row precharge time t
RP
and a row access time t
RAC
which is the amount of time it takes the DRAM to present data on the data bus DQ after a row address has been latched into the DRAM in response to the row address strobe signal {overscore (RAS)} going low. The row access time t
RAC
includes the time it takes the DRAM to latch, decode, and activate the row of memory cells corresponding to the row address ROWX. Also shown in
FIG. 1
is a column access time t
CAC
corresponding to the time it takes the DRAM to present data on the data bus DQ after the column address strobe signal {overscore (CAS)} goes low. The column access time t
CAC
includes the time it takes the DRAM to latch, decode and access the column of memory cells corresponding to the column address COLM. As seen in the signal timing diagram, the column access time t
CAC
is much shorter than the row access time t
RAC
due to the inherent nature of activating an addressed row of memory cells in the memory-cell array versus accessing an addressed memory-cell in one of the columns within the activated row as known in the art.
Various modes of operation for DRAMs have been developed to take advantage of the shorter column access time t
CAC
and thereby increase the bandwidth of the DRAM. One such mode of operation is known as Fast Page Mode and is illustrated in the signal timing diagram of FIG.
2
. In Fast Page Mode operation, each row of memory cells is designated a page and data is read from or written to random columns of memory cells contained in an activated page. The increased bandwidth of Fast Page Mode operation is realized by exploiting the much shorter column access time t
CAC
when compared to the row access time t
RAC
as previously discussed. In Fast Page Mode operation, the external circuit places an initial row address ROWX on the address bus ADDR and drives the row address strobe signal {overscore (RAS)} low at time t
0
to latch the row address ROWX in the DRAM. The external circuit then places an initial column address COLM on the address bus ADDR and drives the column address strobe signal {overscore (CAS)} low at a time t
1
to latch the column address COLM in the DRAM. As previously described, the DRAM decodes the row and column addresses and at a time t
2
places the corresponding data D
1
on the data bus DQ.
Up to time t
2
, the Fast Page Mode read operation is identical to the conventional read operation previously described with reference to FIG.
1
. In contrast to the conventional read operation, however, at time t
2
the external circuitry maintains the row address strobe signal {overscore (RAS)} low keeping the initial addressed row ROWX activated. The external circuit thereafter drives and maintains the column address strobe signal {overscore (CAS)} high for at least a column precharge time t
CP
. The column precharge time t
CP
is the time during which various circuits in the DRAM are precharged and equilibrated in anticipation of placing on the data bus DQ t
Dorsey & Whitney LLP
Ho Hoai V.
Micro)n Technology, Inc.
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