Method and circuit for measuring the read operation delay on DRA

Details Method and circuit for measuring the read operation delay on DRA Method and circuit for measuring the read operation delay on DRA

1999-05-17

2000-07-11

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Signals

365201, 36523006, 365210, G11C 700

Patent

active

060882735

ABSTRACT:
A circuit and a method for measuring the read operation delay on DRAM bit lines are disclosed. The circuit comprises a plurality of circuit blocks connected in series, each having a 1-bit DRAM cell. The output of the DRAM cell in each circuit block is connected to the word line of the DRAM cell of the next circuit block through inverters, so the read operation in the DRAM cell of the next circuit block is triggered. The total delay between the word line at the first circuit block and the output of the last circuit block can be measured on the oscilloscope. The delay for every 1-bit DRAM cell is equal to the total delay divided by the number of circuit blocks.

REFERENCES:
patent: 5901096 (1999-05-01), Inokuchi et al.
patent: 5943288 (1999-08-01), Jiang
patent: 5946243 (1999-08-01), Sim

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