Method and circuit for loading data and reading data

Details Method and circuit for loading data and reading data Method and circuit for loading data and reading data

2000-05-31

2002-07-16

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S233100, C365S233100

Reexamination Certificate

active

06421280

ABSTRACT:

FIELD
The invention generally relates to the loading and reading of data from a plurality of data buffers and, more particularly, relates to a method and circuit for asynchronously loading a plurality of data buffers and synchronously reading from the plurality of data buffers.
BACKGROUND
High-speed microprocessors require low memory latency and high memory bandwidth to reach maximum processing capability. However, high-speed memory capable of keeping up with the processor is very expensive and therefore an approach of using a combination of expensive high-speed memory and less expensive lower-speed memory may be used. High-speed memory, such as cache memory, contains a subset of the data stored in the lower-speed memory. The processor requests data first from the cache, which supplies the data if the data is contained in the cache (cache hit). If the cache does not contain the data (cache miss), the processor retrieves the data from lower-speed memory and also writes the data to the cache for future requests. Since the number of cycles required to retrieve data from lower-speed memory is an order of magnitude larger than the number of cycles to retrieve data from the cache memory, it is desirable to have a high hit rate.
Cache latency is the number of cycles from when the processor requests data from the cache to the time when the first burst of data from cache memory is delivered to the processor. High processor frequencies force latency cycles to increase to allow the cache enough time to determine if an access is a hit or miss and supply the requested data. Bandwidth is the amount of data that can be transferred to the processor measured in bytes of data per second. Bandwidth is independent of latency; a cache memory bus can have a high latency number and still be completely saturated with data yielding a high data bandwidth.
High latency creates a problem storing data that still needs to be burst out to the processor while a new access needs to store its data. The higher the latency, the more difficult this problem can become. To solve this problem, multiple storage buffers may be used. Data may be kept in storage buffers while waiting to be burst out while a separate storage buffer is loaded with data from a subsequent request.


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