Method and circuit for improving metastable resolving time in lo

Details Method and circuit for improving metastable resolving time in lo Method and circuit for improving metastable resolving time in lo

1996-02-27

1998-08-04

Hudspeth, David R.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Metastable state prevention

326 21, 326 93, 327215, H03K 19003

Patent

active

057899452

ABSTRACT:
A circuit and method for improving the metastable resolving time in low-power multi-state devices, including binary latches in integrated circuits. Upon detection of a metastable condition at the outputs of the integrated circuit, an increase in energy is locally applied to the decision making portion of the circuit. The localized application of energy to the decision making circuit reduces the metastability time constant tau (.tau.), thereby causing the circuit to resolve more rapidly to a stable operating state.

REFERENCES:
patent: 4963772 (1990-10-01), Dike
patent: 5001371 (1991-03-01), Mahabadi
patent: 5036221 (1991-07-01), Brucculeri et al.
patent: 5081377 (1992-01-01), Freyman
patent: 5187385 (1993-02-01), Koike
patent: 5365122 (1994-11-01), Rackley
patent: 5485112 (1996-01-01), Greenberg et al.
patent: 5489865 (1996-02-01), Colvin, Sr.

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