Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-08-29
2004-03-30
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230060
Reexamination Certificate
active
06714462
ABSTRACT:
TECHNICAL FIELD
The present invention relates, generally, to memory systems. More particularly, the present invention relates to an output buffer, such as may be utilized for memory applications.
BACKGROUND OF THE INVENTION
In the efforts for optimizing and creating new operations in various high-speed microcontroller-based devices, such as portable personal computers (PCs), personal digital assistants (PDAS) and the like, significant attention has been given to the further improvement of memory devices.
Most new microprocessor-based applications are configured for high processing speed through implementation of dynamic random access memory (DRAM) devices, including synchronous dynamic random access memory (SDRAM) devices that can operate at significantly higher clock speeds than conventional memory devices. In particular, SDRAM devices are synchronized with the clock speed in which the microprocessor is optimized, thus enabling the number of instructions that the microprocessor can perform at a given time to be increased.
With reference to
FIGS. 1A and 1B
, an output buffer
100
as may be implemented within an SDRAM device comprises a pair of predriver circuits
102
and
104
and output driver devices
106
. A control logic and pull-up predriver circuit
102
is provided for controlling and driving a pull-up transistor M
P0
, while a control logic and pull-down predriver circuit
104
is provided for controlling and driving a pull-down transistor M
N0
. Pull-up/down transistors M
P0
and M
N0
are further connected to a bondpad
108
. Control logic and predriver circuits
102
and
104
can be configured with an internally supplied voltage V
CCR
(or I/O power supply V
CCQ
) to drive the gates of pull-up/down transistors M
P0
and M
N0
to provide an output signal.
An important characteristic in the design and operation of DRAM devices is the slew rate performance of the output buffers within the DRAM devices. The slew rate is the rate from which the output from an electronic circuit or device can be driven from one limit to another over the dynamic range of the electronic circuit or device. For DRAM devices, an ideal slew rate is between approximately 2 to 4 volts
anosecond. The slew rate of the output signal of the output buffers in DRAM applications can significantly affect various timing specifications, including TAC, TDQSQ, and the like. As a result, it is desirable for the slew rate to be relatively constant for such output buffers.
Unfortunately, the slew rate of the output signal of such output buffers is often varied by the power supply, as well as process and temperature variations within the DRAM device. Of these reasons, changes in the power supply is the biggest impediment to constant slew rate operation. For example, for a change in power supply voltage from 2.3 volts to 2.7 volts, the slew rate of the output signal can vary by approximately 40-50% or more.
SUMMARY OF THE INVENTION
In accordance with various aspects of the present invention, a memory system includes an output buffer with an output signal having a substantially constant slew rate. In accordance with an exemplary embodiment, the output buffer comprises a slew rate control circuit and an output driver circuit. The slew rate control circuit is configured at the input terminals of the output driver circuit, for example between a predriver circuit and the output driver circuit. The slew rate control circuit is configured to suitably control the slew rate of an input signal for the output driver circuit, for example an input signal provided by a predriver circuit, based on the level of voltage of a power supply for the output driver circuit. For increases in the voltage of the power supply, the slew rate of the input signal of the output driver circuit is decreased by the slew rate control circuit, while for decreases in the voltage of the power supply, the slew rate of the input signal of the output driver circuit is increased by the slew rate control circuit. As a result of controlling the slew rate of the input signal of the output driver circuit, the variation of the slew rate of the output signal of the output buffer is significantly reduced.
In accordance with an exemplary embodiment, the slew rate control circuit comprises a first amplifier circuit for controlling the slew rate of an input signal provided to a pull-up element of the output driver circuit, and a second amplifier circuit for controlling the slew rate of an input signal provided to a pull-down element of the output driver circuit. The amplifier circuits can also be configured with current sources configured to facilitate control of the slew rate of the input signals provided to the pull-up and pull-down elements of the output driver circuit based on the level in voltage in the power supply. In an exemplary embodiment, the amplifier circuits comprise operational transconductance amplifiers (OTA's) having voltage-controlled current sources configured for controlling the biasing current for the OTA's based on the level in voltage in the power supply.
REFERENCES:
patent: 5191269 (1993-03-01), Carbolante
patent: 5568081 (1996-10-01), Lui et al.
patent: 6236248 (2001-05-01), Koga
Micro)n Technology, Inc.
Snell & Wilmer L.L.P.
Tran M.
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