Method and circuit for detecting a spurious lock signal from a l

Details Method and circuit for detecting a spurious lock signal from a l Method and circuit for detecting a spurious lock signal from a l

1997-12-08

2000-09-05

Bocure, Tesfaldet

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

H04L 700

Patent

active

061154385

ABSTRACT:
A method and circuit for detecting a spurious lock signal from a lock detect circuit are disclosed. The method includes generating a lock signal (16, 58, 84) having two states: lock and unlock. The lock signal (16, 58, 84) is monitored at a debounce circuit (50, 80). A reference clock signal (56, 86) is then received at the debounce circuit (50, 80). A clean lock signal (68, 88) is generated by the debounce circuit (50, 80) when the lock state of the lock signal (16, 58, 84) is received for at least two cycles of the reference clock. If the lock state of the lock signal (16, 58, 84) is received for less than two cycles of the reference clock, a clean loss-of-lock signal (68, 88) is generated. The circuit for detecting a spurious lock signal (50, 80) includes a lock detect circuit for generating a lock signal (10) and a plurality of flip-flops (70, 72, 92, 94, 96, 98). Each flip-flop (70, 72, 92, 94, 96, 98) has a data input (54, 82), a clock input (60, 106), a clear input (62, 102) for receiving the lock signal, and a data output (66, 108). A reference clock signal (56, 86) is connected to the clock input (60, 106) of each flip-flop (70, 72, 92, 94, 96, 98). The circuit further includes a clear lock signal output (68, 88).

REFERENCES:
patent: 5483558 (1996-01-01), Leon et al.
patent: 5889828 (1999-03-01), Miyashita et al.

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