Method and circuit for detecting a fault in a clock signal for m

Details Method and circuit for detecting a fault in a clock signal for m Method and circuit for detecting a fault in a clock signal for m

1995-03-31

1997-02-25

Dinh, Son T.

Static information storage and retrieval

Addressing

Sync/clocking

365191, G11C 800

Patent

active

056065310

ABSTRACT:
An electronic device including a microprocessor, a circuit generating a clock signal, and memories of both the volatile type and the non-volatile type, incorporates a circuit for generation of a reset signal capable of detecting a stop in the oscillation of said clock signal and generating a logic signal coupled with the reset input of the microprocessor. The circuit monitors the clock signal applied to the device and, if an irregularity is detected, generate a reset signal holding the microprocessor in a safe state. The reset signal is held until the circuit generating the clock signal resumes normal operation.

REFERENCES:
patent: 4633097 (1986-12-01), Dewitt et al.
patent: 4802131 (1989-01-01), Toyoda
patent: 5018111 (1991-05-01), Madland
patent: 5199032 (1993-03-01), Sparks et al.
CA IBM Technical Disclosure Bulletin, vol. 37 No. 04B, Apr. 1994, pp. 185-188.

Affiliated with

Also associated with

Rating

Method and circuit for detecting a fault in a clock signal for m does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and circuit for detecting a fault in a clock signal for m, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and circuit for detecting a fault in a clock signal for m will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1979074