Method and circuit for controlling an isolation gate in a semico

Details Method and circuit for controlling an isolation gate in a semico Method and circuit for controlling an isolation gate in a semico

1998-02-05

1999-09-28

Nelms, David

Static information storage and retrieval

Read/write circuit

Data refresh

36523003, 36523006, 36523008, G11C 700

Patent

active

059599243

ABSTRACT:
A method of controlling an isolation gate of a semiconductor memory device and a circuit therefor are disclosed. The method includes the steps of generating a refresh row active signal, generating a plurality of block select signals, generating a latch isolation control signal and controlling an isolation gate. The refresh row active signal is activated for a constant period. A plurality of block select signals are selectively activated when the refresh row active signal is active. The latch isolation control signal is set according to a block select signal and reset by an adjacent block select signal related to the other isolation gate connected to the same bit line sense amplifier of the block. In the step of controlling the isolation gate, when the latch isolation control signal is active, the isolation gates are turned on, and the other isolation gates connected to the same bit line sense amplifier are turned off. The isolation gate control circuit includes a plurality of latches, a plurality of block select signal drivers and a plurality of isolation gate control signal generators.

REFERENCES:
patent: 5251176 (1993-10-01), Komatsu
patent: 5798976 (1998-08-01), Arimoto
patent: 5822264 (1998-10-01), Tomishima et al.
patent: 5831921 (1998-11-01), Tsukude
patent: 5831924 (1998-11-01), Nitta et al.
patent: 5835436 (1998-11-01), Ooishi
patent: 5835441 (1998-11-01), Seyyedy et al.
patent: 5844849 (1998-12-01), Furutani

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