Method and circuit for collecting memory failure information

Details Method and circuit for collecting memory failure information Method and circuit for collecting memory failure information

2008-05-06

2008-05-06

Kerveros, James C. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

10690594

ABSTRACT:
A method and circuit for collecting memory failure information on-chip and unloading the information in real time while performing a test of memory embedded in a circuit comprises, for each column or row of a memory under test, testing each memory location of the column or row according to a memory test algorithm under control of a first clock, selectively generating a failure summary on-circuit while testing each column or row of the memory; and transferring the failure summary from the circuit under control of a second clock within the time required to test the next column or row, if any, of the memory under test.

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Chen et al., “Test Response Compression and Bitmap Encoding for Embedded Memories in Manufacturing Process Monitoring”, 2001 ITC Proceedings. p. 258.

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