Method and circuit for accessing an integrated semiconductor mem

Details Method and circuit for accessing an integrated semiconductor mem Method and circuit for accessing an integrated semiconductor mem

1981-07-06

1983-09-13

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

365154, G11C 1140

Patent

active

044046626

ABSTRACT:
A memory system is provided having an array of cells, each of which may include first and second cross-coupled inverting NPN transistors and first and second PNP transistors for injecting charge into the first and second inverting transistors. A first bit/sense line of a bit/sense line pair is connected to the emitter of the first inverting transistor and a second bit/sense line of the pair is connected to the emitter of the second inverting transistor and a common word line is connected to the emitters of the first and second charge injecting transistors. To read a selected cell, all cells of the array are discharged through the word lines, the pair of bit/sense lines connected to the selected cell are electrically floated or isolated and the word line connected to the selected cell is energized by a word driver. The signal developed in the bit/sense lines connected to the selected cell is detected while the word line connected to the selected cell is being energized by the word driver.

REFERENCES:
patent: 3832699 (1974-08-01), Matsue
patent: 4090255 (1978-05-01), Berger et al.
patent: 4158237 (1979-06-01), Wiedmann
patent: 4280198 (1981-07-01), Heuber et al.
patent: 4319344 (1982-03-01), Heuber et al.

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