Method and circuit arrangement for memory error processing

Details Method and circuit arrangement for memory error processing Method and circuit arrangement for memory error processing

2007-02-20

2007-02-20

Baderman, Scott (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S006130, C714S042000

Reexamination Certificate

active

10481570

ABSTRACT:
The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are recorded redundantly by applying a corresponding coding. Then, an error correction is applied to the faulty-address information before it is compared to an externally applied address. Thereby, errors due to faulty redundancy addresses can be prevented.

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patent: 5996096 (1999-11-01), Dell et al.
patent: 6404683 (2002-06-01), Yumoto
patent: 6601194 (2003-07-01), Dahn et al.

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