Method and circuit arrangement for discharging bit line capacita

Details Method and circuit arrangement for discharging bit line capacita Method and circuit arrangement for discharging bit line capacita

1980-05-30

1982-03-09

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

365154, G11C 1300

Patent

active

043193447

ABSTRACT:
A method and arrangement is provided for selecting and discharging a pair of bit lines of a plurality of charged pairs of bit lines of a memory circuit having cells of the merged transistor logic type. A selected pair of bit lines is discharged through a selected cell coupled to the selected pair of bit lines while simultaneously the remaining or non-selected pairs of bit lines are discharged through a common switch into non-selected word lines.

REFERENCES:
patent: 3736477 (1973-05-01), Berger et al.
patent: 3815106 (1974-06-01), Weidmann
patent: 3816758 (1974-06-01), Berger et al.
patent: 4044341 (1977-08-01), Stewart
patent: 4077031 (1978-02-01), Kitagawa
patent: 4090255 (1978-05-01), Berger et al.
patent: 4110840 (1978-08-01), Abe et al.
IEEE Journal of Solid State Circuits, vol. SC/7, No. 5, Oct. 1972, pp. 340-346.

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