Method and auxiliary device for testing a RAM memory circuit

Details Method and auxiliary device for testing a RAM memory circuit Method and auxiliary device for testing a RAM memory circuit

2007-10-02

2007-10-02

Lamarre, Guy (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S719000

Reexamination Certificate

active

10429579

ABSTRACT:
The testing of a RAM memory circuit containing a multiplicity of memory cells can in each case be selected in groups of n≧1 memory cells by using an applied address information item in order to write in or read out groups of in each case n data. According to the invention, in a test write cycle, a plurality i=j*m of the memory cell groups are selected, where j and m are in each case integers ≧2, and the same datum is written into all the memory cells of in each case m selected memory cell groups. In a subsequent read cycle, the i memory cell groups selected in the write cycle are selected and read in a sequence such that the read-out data groups from in each case m memory cell groups at which the same datum was written in are provided simultaneously or in direct succession as a read data block comprising m*n data. Each time a read data block is provided, a compressed test result is determined and provided; the result indicates if all m*n data of the read data block provided correspond to the datum written therein.

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