Method and arrangement for reducing source/drain resistance...

Details Method and arrangement for reducing source/drain resistance... Method and arrangement for reducing source/drain resistance...

2007-02-27

2007-02-27

Lindsay, Jr., Walter (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S306000, C257SE29027, C257S021000

Reexamination Certificate

active

11072312

ABSTRACT:
A method and arrangement for reducing the series resistance of the source and drain in a MOSFET device provides for epitaxially grown regions on top of the source and drain extensions to cover portions of the top surfaces of the silicide regions formed on the substrate. The epitaxial material provides an extra flow path for current to flow through to the silicide from the extension, as well as increasing the surface area between the source/drain and the silicide to reduce the contact resistance between the source/drain and the silicide.

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