Method and architecture to prevent corrupt data propagation...

Details Method and architecture to prevent corrupt data propagation... Method and architecture to prevent corrupt data propagation...

2011-08-30

2011-08-30

Abraham, Esaw T (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S807000, C370S394000, C710S310000

Reexamination Certificate

active

08010860

ABSTRACT:
A PCI Express compliant method and apparatus for preventing corrupt data being transmitted from a retry buffer of a transmitting component to a receiving component over a PCI Express compliant link. The method including storing parity or electronic error correction bits for each data entry in the retry buffer along with the data itself and then comparing parity or electronic error correction bits generated from a copy of the data from the retry buffer to the parity or electronic error correction bits stored in the retry buffer. If the two sets of bits do not match, a PCI Express link between the transmitting component to a receiving component is forced down.

REFERENCES:
patent: 7152136 (2006-12-01), Charagulla
patent: 7191255 (2007-03-01), Wong et al.
patent: 7424567 (2008-09-01), Manula et al.
patent: 7457897 (2008-11-01), Lee et al.
patent: 7769048 (2010-08-01), Sharma
patent: 7792014 (2010-09-01), Tsang
PCI Express Base Specification Revision 2.0; Dec. 20, 2006; PCI Express; 608 pages.
PHY Interface for the PCI Express Architecture; Version 1.00; Jun. 19, 2003 9:22 AM; PIPE Macro 1—00.doc; 2003 Inter Corporation; 31 pages.

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