Method and architecture for detecting random and systematic...

Details Method and architecture for detecting random and systematic... Method and architecture for detecting random and systematic...

2005-12-20

2005-12-20

Ton, David (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S732000

Reexamination Certificate

active

06978407

ABSTRACT:
A self-aligning memory cell design is provided to allow testing of transistors in every cell of a memory circuit. A test array of these cells is fabricated with contact pads in each cell for specific components in the cell. Then, metal lines are provided to couple the contact pads in the test array. The whole test array is then probed via these metal lines. Tests may then be performed to detect random and systematic transistor degradation electrically for all cells in the circuit. Different components in the memory design may be tested by providing contact pads for the components of interest and providing metal lines coupling the contact pads.

REFERENCES:
patent: 6235575 (2001-05-01), Kasai et al.
patent: 6447339 (2002-09-01), Reed et al.
patent: 6636058 (2003-10-01), Lyford
patent: 6639859 (2003-10-01), Tran
patent: 6781391 (2004-08-01), Reed et al.

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