Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-02-18
2001-06-26
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S714000, C438S715000, C438S725000, C438S745000
Reexamination Certificate
active
06251794
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the fabrication of integrated circuit devices, and more particularly to a method and an apparatus for eliminating of photoresist extrusions (photoresist bubbles) formed in the post dry ash bond pad alloy operation.
DESCRIPTION OF THE PRIOR ART
Integrated Circuit Manufacture
Integrated circuits are formed upon semiconductor substrates from semiconductor devices, such as field effect transistors (FETs) and/or bipolar transistors, diodes, resistors as well as other electrical devices which are typically electrically interconnected using multiple layers (usually two to four) of patterned conductor materials, such as metal, refractory metal silicides and doped polysilicon.
Each layer of patterned conductor is separated by a layer of insulating material such as silicon oxide (SiO
2
) typically deposited by chemical vapor deposition (CVD) methods, over each patterned conductor to insulate it from the next layer of patterned conductor.
Via holes in each layer of the insulating material are patterned by etching methods to expose portions of the electrical devices and/or the prior patterned conductor to the next layer of patterned conductor. In this manner all layers of patterned conductor are interconnected to form the required wired circuits and function of the integrated circuit.
Using the
FIG. 2
as an example, a final layer of conducting material, typically composed of an aluminum or an aluminum/copper alloy on a substrate
1
(the underlying layers not shown) suitable for bonding external wiring, is patterned in a standard array of bond pads
2
for subsequent connection to the signal inputs and outputs (IOs) and the electrical power and ground sources on a single or a multiple chip carrier.
The substrate, made of semiconductor material, with the internal devices, multi-level of interconnection wiring and the array of bond pads is passivated, to insulate the final layer of conducting material and to physically protect the integrated circuit.
In a conventional method,
FIG. 10
, a first layer of passivation
3
is typically formed by chemical vapor deposition (CVD) of an blanket insulating material, which is patterned etched
101
to form contact openings
4
exposing the bond pads
2
.
The next major operation upon the substrate in the integrated circuit manufacturing process is an alloy step
104
which is typically performed upon the array of bond pads to assure low contact resistance with the bond pads.
The present invention in particular, hereinafter discussed, addresses the photoresist removal operations prior to the alloy operation
104
to eliminate a defect
5
.
A second, thicker passivation layer
6
, shown within the dotted lines in
FIG. 2
, usually a photosensitive polyimide, is then applied to the substrate to provide additional insulation and physical protection for the integrated circuits as the substrate is subsequently tested, diced into individual chips, the chips mounted in chip carriers and the bond pads connected to chip carrier I/Os.
Photoresist Operations
Throughout the semiconductor manufacturing process photolithographic operations are called upon to realize the semiconductor device structures and their multilevel interconnections from photomask images through the use of a photoresist medium
7
which is patterned
8
as exemplified in FIG.
1
.
The patterned photoresist
8
, shown in
FIG. 1
, performs the task of protecting the underlying material from reaction to the subsequent process, such as etching of conductor or insulator materials and ionization doping of semiconductor materials.
Photoresists in liquid form are usually spin coated on the semiconductor substrate and are prepared for the photolithographic operation. The photoresist is exposed with a certain wavelength of light to an image on the photomask, typically in a step and repeat align and expose apparatus. Exposure of the photoresist to this image pattern hardens the resist into the desired latent pattern. A photoresist developing process, typically a wet chemical treatment, removes the unhardened resist leaving a pattern of resist protecting the underlying material for the subsequent major manufacturing process step. Photolithographic operations include the use of positive and negative photomasks, positive and negative photoresists, projection and contact printing with a range of exposure wavelengths and a variety of photoresist developing processes.
Typically, this patterned photoresist
8
is then removed by a wet chemical treatment
102
and/or oxygen plasma dry ash
103
to present a fully patterned underlying layer of conductor, semiconductor or insulation material.
Manufacturing Defects
Defects occur at any of the processing steps in the manufacture of a semiconductor integrated circuit and are characterized as to where, when and how they occurred, such as pin holes in a blanket insulation layer, defect in a photomask, or contamination in the wet treatment chemicals, and as to whether they are fatal, repairable or cosmetic defects.
Usually, after one or more semiconductor manufacturing steps a quality control inspection, a staged inspection or an in process inspection is undertaken to reveal defects attributable to the prior processes, to assure maintaining manufacturing process tolerances, to rework or to scrap the substrate and to assure quality of the integrated circuit. Discovery of a defect by inspection and proposed theory of their generation give rise to instituting new methods of process to preclude future generation of the defect.
Refer to FIG.
2
. The particular defect remedied by the present invention is a photoresist extrusion
5
or photoresist bubble caused by incomplete removal
102
and
103
of photoresist after the passivation layer etching step. Again refer to FIG.
1
. The first passivation layer
3
is typically 7000-12000 Angstroms thick and it follows the topography of the underlying metal conductor patterns
2
and
9
, which is typically 4000-8000 Angstroms thick, giving rise to passivation keyholes
10
, in the overlying passivation layer entrapping photoresist material
5
which is not removed during the photoresist removal steps of wet stripping
102
and dry ashing with oxygen plasma
103
. The defect is not observable after the oxygen plasma dry ash
103
, but can be observed after the alloy step
104
. The defect is theorized to be due to the photoresist residue extruding from the keyholes
10
due to the subsequent alloy step
104
performed at 450 degrees Centigrade. The conventional remedy for the removal of this post alloy extruded photoresist residue is to subject the substrate to a second oxygen plasma ash step
105
.
The keyholes
10
, as illustrated in proportional cross-sectional detail in
FIG. 13
are small cavities generated in the passivation layer
3
as it is continually deposited in regions of close metal conductor
9
spacing. The passivation layer
3
growth is not uniform within a narrow gap between metal conductor features
9
and the resulting cavity extending to the passivation layer
3
surface is formed parallel to the metal conductors
9
. When photoresist is applied to the surface, it penetrates into these keyholes
10
, yet neither wet stripping nor dry ashing is effective in completely removing the photoresist prior to alloy step
104
.
In general this type of defect, imbedded photoresist, may be found relative to other types of defects in any of the interconnecting insulator or conductor layers, namely pinholes or small voids in the blanket insulating or conductor material in which is imbedded some of the overlying patterned photoresist.
Specific Prior Art
The following prior art, presented chronologically, discusses the utilization of different wet chemical treatment, dry ash and substrate heating techniques employed in methods of photoresist removal to eliminate other specific defects or problems.
Refer to
FIGS. 5 and 6
. U.S. Pat. No. 5,226,056 (1993 Kikuchi et al.) addresses the need to use patterned photoresist materials directly, early in the manufacturing process, fo
Lin Ching-Chung
Peng Chiang-Jen
Ackerma Stephen B.
Saile George O.
Taiwan Semiconductor Manufacturing Company
Tran Binh X.
Utech Benjamin L.
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