Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1999-01-21
2001-05-08
Gaffin, Jeffrey (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S260000
Reexamination Certificate
active
06229100
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to components useful for the mounting of semiconductor chips and related electronic components, to assemblies made using such components and to methods of making such components and assemblies.
BACKGROUND OF THE INVENTION
Modern electronic devices utilize semiconductor chips, commonly referred to as “integrated circuits” which incorporate numerous electronic elements. These chips are mounted on substrates which physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be a part of a discrete chip package used to hold a single chip and equipped with terminals for interconnection to external circuit elements. Such substrates may be secured to an external circuit board or chassis. Alternatively, in a so-called “hybrid circuit” one or more chips are mounted directly to a substrate forming a circuit panel arranged to interconnect the chips and the other circuit elements mounted to the substrate. In either case, the chip must be securely held on the substrate and must be provided with reliable electrical interconnection to the substrate. The interconnection between the chip itself and its supporting substrate is commonly referred to as “first level” assembly or chip interconnection, as distinguished from the interconnection between the substrate and the larger elements of the circuit, commonly referred to as a “second level” interconnection.
The structures utilized to provide the first level connection between the chip and the substrate must accommodate all of the required electrical interconnections to the chip. The number of connections to external circuit elements, commonly referred to as “input-output” or “I/O” connections, is determined by the structure and function of the chip. Advanced chips capable of performing numerous functions may require substantial numbers of I/O connections.
The size of the chip and substrate assembly is a major concern. The size of each such assembly influences the size of the overall electronic device. More compact assemblies, with smaller distances between chips provide smaller signal transmission delays and hence permit faster operation of the device.
First level interconnection structures connecting a chip to a substrate ordinarily are subject to substantial strain caused by thermal cycling as temperatures within the device change during operation. The electrical power dissipated within the chip tends to heat the chip and substrate, so that the temperatures of the chip and substrate rise each time the device is turned on and fall each time the device is turned off. As the temperatures change, the chip and substrate may expand and contract by different amounts. This causes the electrical contacts on the chip to move relative to the electrical contact pads on the substrate. This relative movement deforms the electrical interconnections between the chip and substrate and places them under mechanical stress. These stresses are applied repeatedly with repeated operation of the device, and can cause breakage of the electrical interconnections.
Further, the insertion of a chip into a socket or connector, either for testing or for permanent bonding in an application package, may cause significant stresses on the electrical interconnections and within the chip. Such stresses are created by imperfect geometries of the connection arrays, such as pitch error, by shock or impact during insertion, as well as by positioning error of the chip with respect to the connector. Those stresses are often in a horizontal plane, parallel to the facing surfaces of the chip and the connector.
Despite all of the efforts made during manufacture of the chips, some chips will be defective. These defects often cannot be detected until the chip is operated under power in a test fixture or in an actual assembly. A single bad chip can make a larger assembly including numerous chips and other valuable components worthless, or can require painstaking procedures to extricate the bad chip from the assembly. Therefore, the chips and the mounting components used in any chip assembly system should permit testing of chips and replacement of defective chips before the chips are fused to a substrate. The cost of the chip and substrate assembly is also a major concern.
All these concerns, taken together, present a formidable engineering challenge. Various attempts have been made heretofore to provide first-level interconnection structures and methods to meet these concerns. At present, the most widely utilized primary interconnection methods are wire bonding, tape automated bonding or “TAB” and flip-chip bonding.
In wire bonding, the substrate has a top surface with a plurality of electrically conductive contact pads or lands disposed in a ring-like pattern. The chip is secured to the top surface of the substrate at the center of the ring-like pattern, so that the chip is surrounded by the contact pads on the substrate. The chip is mounted in a face-up disposition, with the back surface of the chip confronting the top surface of the substrate and with the front surface of the chip facing upwardly, away from the substrate, so that electrical contacts on the front surface are exposed. Fine wires are connected between the contacts on the front face of the chip and the contact pads on the top surface of the substrate. These wires extend outwardly from the chip to the surrounding contact pads on the substrate. In wire bonded assembly, the area of the substrate occupied by the chip, the wires and the contact pads of the substrate is substantially greater than the surface area of the chip itself. Moreover, the wire bonding process does not provide any pre-testing of the chip. Thus, the bare chip must be tested using separate equipment before the wire bonding process. Testing a bare chip poses numerous practical difficulties. It is therefore difficult to make reliable low inductance electrical connections with all of the contacts on the chip simultaneously. Elder et al, U.S. Pat. No. 5,123,850 and Jameson et al, U.S. Pat. No. 4,783,719 disclose chip testing fixtures in which conductive elements on a flexible device are pressed against electrical contacts of the chip.
In the TAB process, a polymer tape is provided with thin layers of metallic material forming conductors on a first surface of the tape. These conductors are arranged generally in a fan-out pattern and extend generally radially, away from the center of the pattern. The chip is placed on the tape in a face down arrangement, with contacts on the front surface of the chip confronting the conductors on the first surface of the tape. The contacts on the chip are bonded to the conductors on the tape. Because the leads utilized in tape automated bonding extend outwardly in a radial, fan-out pattern from the chip, the assembly is much larger than the chip itself. Enochs, U.S. Pat. No. 4,597,617 and Matta et al, U.S. Pat. No. 5,053,922 disclose variants of the TAB process in which the outer ends of the leads on the tape are placed in contact with the substrate by mechanical pressure, rather than by metallurgical bonding.
In flip-chip bonding, contacts on the front surface of the chip are provided with bump leads such as balls of solder protruding from the front surface of the chip. The substrate has contact pads arranged in an array corresponding to the array of contacts on the chip. The chip, with the solder bumps, is inverted so that its front surface faces toward the top surface of the substrate, with each contact and solder bump on the chip being positioned on the appropriate contact pad of the substrate. The assembly is then heated so as to liquefy the solder and bond each contact on the chip to the confronting contact pad of the substrate. Because the flip-chip arrangement does not require leads arranged in a fan-out pattern, it provides a compact assembly. The area of the substrate occupied by the contact pads is approximately the same size as the chip itself. Moreover, in flip-chip bonding, the contacts on the chip may be
Gaffin Jeffrey
Lerner David Littenberg Krumholz & Mentlik LLP
Norris Jeremy
Tessera Inc.
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