Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-12-21
2003-09-30
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S718000
Reexamination Certificate
active
06629274
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to testing the correct operation of integrated circuits; more particularly, the present invention relates to testing an input/output circuit in an integrated circuit.
BACKGROUND
Before an integrated circuit (IC) may be used in an application, it is typically necessary to verify the proper functionality and timing of components within each input/output (I/O) circuit (or buffer) of the IC. Verifying the functionality of an IC is typically accomplished by placing the IC on a tester that includes a tester channel for each I/O pin on the IC. Subsequently, each I/O buffer coupled to an I/O pin is tested for functionality, timing, performance, etc.
One type of test that is used to verify the functionality of IC components is a switching state (AC) timing functionality test. The AC functionality test is used to test the AC timing specifications of an I/O buffer. In order to detect failures, AC I/O testing typically uses expensive high pin count test equipment with accurate edge placement in order to carry out accurate probing of each pin of an IC. One problem with such tester requirements is the exorbitant costs. Moreover, the improvement in edge placement accuracy of automated test equipment (ATE) have not kept up with the decreasing margins on very high-speed IC interfaces.
Currently, I/O buffers on IC devices are tested with tight timings of ATE that are set tighter than the specifications of the integrated circuit. Typically, Source Synchronous tight timing tests involve deducing worse case skew from individual measurements that may introduce in excess of 500 Pico seconds of metrology error caused by such an unreliable test method. In addition, the worst case measurement may introduce edge placement accuracy error caused by accuracy limitations of the ATE. However, deducing skew from worse case measurements may effectively preclude testing interfaces that are greater than 300 mts.
As described above, functional testing is typically inefficient since very accurate edge placement capabilities are required. In addition, each signal pin on an integrated circuit must be probed separately. Testing each pin results in an increase in cost of the ATE. Therefore, a method and apparatus for efficiently conducting AC I/O loopback testing at I/O buffers is desired.
SUMMARY OF THE INVENTION
According to one embodiment, an integrated circuit includes a first input output (I/O) buffer for generating strobe clock pulses and a second I/O buffer coupled to the first I/O buffer. The generation of strobe clock pulses is varied with respect to test data received at the second I/O buffer during switching state (AC) loopback tests.
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Frodsham R. Tim
Ilkbahar Alper
Mak Tak M.
Tripp Mike
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Ton David
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