Method and apparatus to reduce random yield loss

Details Method and apparatus to reduce random yield loss Method and apparatus to reduce random yield loss

2007-03-16

2009-06-02

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07543255

ABSTRACT:
One embodiment of the present invention provides a system that reduces random yield loss. During operation, the system can receive a design layout. The system may also receive weighting factors that are associated with the particle densities in the metal regions and the empty regions. Next, the system can determine local critical-area-ratios and optimization potentials for a set of wire-segments. The system can then select a wire segment, and compare its local critical-area-ratio with a global critical-area-ratio. Next, the system can use the result of the comparison to determine a layout optimization. The system can then apply the layout optimization to the wire segment to obtain an improved layout.

REFERENCES:
patent: 6691293 (2004-02-01), Kanazawa
patent: 7346865 (2008-03-01), Su et al.
patent: 2006/0095877 (2006-05-01), Su
patent: 2007/0028201 (2007-02-01), Mehrotra et al.
Subarna Sinha et al., A New Flexible Algorithm for Random Yield Improvement, Proceedings of the 8th International Symposium on Quality Electronic Design (ISQED'07) 0-7695-2795-7/07 IEEE.
Jin-Tai Yan et al., Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization, 20th International Conference on VLSI Design (VLSID'07) 0-7695-2762-0/07 IEEE.

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