Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2001-06-29
2003-02-11
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S189120, C365S230020
Reexamination Certificate
active
06519202
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit memory devices, and more specifically to a memory having a column redundancy scheme.
BACKGROUND OF THE INVENTION
Random defects occurring during the manufacturing of an integrated circuit memory device can render non-redundant elements of an integrated circuit memory device, such as a memory column, defective. For example, particle contamination during the manufacturing process may cause broken or shorted out columns and bit defects.
Redundant elements in an integrated circuit memory device, such as redundant columns, are used to compensate for these random defects. Initial testing of an integrated circuit memory occurs after the manufacturing process. During initial testing of an integrated circuit memory device, defective elements are replaced by non-defective elements referred to as redundant elements. Thus, redundant columns may be used in a scheme to replace defective non-redundant columns, discovered during initial testing of the integrated circuit memory device. The use of redundant elements is important in increasing the overall yield of an integrated circuit memory device.
With ever increasing densities and smaller feature sizes in integrated circuit memory devices, cell redundancy has become more and more important to the proper functioning of larger memory devices. Most memories now require column redundancy in which a portion of the memory cell array is designated as a redundant memory section. When a defective portion of the main memory exists, then the memory cells of the redundant memory section are accessed. On-chip logic circuitry is employed to store defective main memory column references consisting of bit number and Y-address information to facilitate writing and reading of data to the redundant memory. This logic circuitry includes multiple fuse groups wherein individual fuses within a fuse group are either open or closed to represent a logic state. Each fuse group forms a logic word corresponding to a defective memory column in the main memory. To enable use of the redundant column, a set of fuses are, generally, cut or blown.
Several problems exist in previous techniques to create redundant memory columns. For example, a problem exists in some previous techniques in that the number of the redundant memory columns needs to match the number, (e.g., 8 columns, 16 columns, or 32 columns) of non-redundant memory columns coupled to each input-output circuit. As such, large scale memory column schemes require more space to implement redundant columns. For example, 32 redundant memory columns occupy approximately four times the space that 8 redundant memory columns occupy. This decreases the physical space remaining on the chip that may be used for packing additional operational components onto the single chip. Reducing the physical space that the redundant memory columns occupy decreases the cost per dice to manufacture the die.
FIGS. 1-4
illustrate previous techniques of various memory devices accompanied by fuse boxes associated with that memory device.
FIG. 1
illustrates a previous technique of having an equal number of memory columns coupled to both the redundant and non-redundant memory columns. The memory device contains a redundant input-output circuit, and non-redundant input-output circuits, such as the first input-output circuit (IO[
0
]) through the sixth input-output circuit (IO[
5
]). In this previous technique, the amount of memory columns in the group of non-redundant memory columns coupled to the non-redundant input-output circuit was equal to the amount of memory columns in the group of redundant memory columns coupled to the redundant input-output circuit. For example, non-redundant input-output circuit IO[
0
] couples to a group of eight non-redundant memory columns. The redundant input-output circuit also couples to eight memory non-redundant memory columns. Note that only one fuse is required per input-output circuit because the number of columns coupled the redundant input output circuit is equal to the number of columns coupled to each non-redundant input-output circuit.
FIG. 2
illustrates a previous technique of having a fuse associated with each sub-input-output circuit contained with an input-output circuit. Each non-redundant input-output circuit, such as IO[
0
] contains two sub input-output circuits. For example, non-redundant input-output circuit IO[
0
] contains two sub input-output circuits, sub-IO-
0
and sub-IO-
1
. Non-redundant input-output circuit IO[
0
] couples through sub-IO-
0
and sub-IO-
1
to the group of eight non-redundant memory columns. Each sub input-output circuit has a fuse associated with that particular sub input-output circuit to indicate whether one or more memory columns coupled to that sub input-output circuit are defective. For example, the second fuse is blown indicated by the fuse containing a logical
1
. The second fuse is blown to indicate one or more memory columns coupled to sub-IO-
2
are defective. Thus, in this example, the memory device needs the physical space on a silicon chip for two fuses per input-output circuit because one fuse exists per sub input-output circuit.
FIG. 2
also illustrates a previous technique of a single global input-output select signal going to every sub input-output in each input-output. The global sub input-output enable signal activates all the sub input-output's contained in a single input-output circuit when a reading or writing operation occurs. For example, the global sub-input-output enable signal is received in both sub-IO-
0
and sub-IO-
1
contained in input-output circuit IO[
0
]. The global sub input-output enable signal causes every sub input-output in that particular input-output circuit to activate. When every sub input-output circuit activates each sub input-output circuit consumes power whether or not a data transfer operation is occurring in that particular sub-IO circuit. Reducing power consumption by electronic circuits not in use is a major concern, especially in portable devices powered by a battery.
FIG. 2
also illustrates the previous technique of having an equal number of memory columns coupled to both the redundant and non-redundant memory columns. As noted above, non-redundant input-output circuit IO[
0
] couples through sub-IO
0
and sub-IO
1
to the group of eight non-redundant memory columns. The redundant input-out circuit also couples its two sub input-output circuits to a group of eight memory non-redundant memory columns.
FIG. 3
illustrates a previous technique of having thirty-two memory columns coupled to the redundant input-output circuit as well as having thirty-two, i.e. an equal number of memory columns, coupled to a non-redundant input-output circuit. Also, it should be noted that if the previous technique of having one fuse for each sub input-output circuit contained in an input-output circuit was implemented, then typically four sub input-output circuits would be contained in each input-output circuit. Thus, the memory device needs the physical space on a silicon chip for four fuses per input-output circuit because one fuse exists per sub input-output circuit.
FIG. 3
illustrates a single global sub input-output enable signal going to each sub input-output circuit. Likewise, if four sub input-output circuits existed per input-output circuit, then the global sub input-output enable signal needlessly activated all four sub input-output circuits when only one sub input-output was actually performing a data transfer operation.
FIGS. 4A-1
and
4
A-
2
illustrate a single global sub input-output enable signal going to both the sub input-output circuits, sub-IO-
0
and sub-IO-
1
, contained in input-output circuit IO[
2
]. The global sub input-output enable signal activates both sub input-output circuits when performing data transfer operation, such as a reading operation to a memory column in the group of memory columns coupled to the input-outpu
Behera Niranjan
Kense Izak
Shubat Alexander
Blakely , Sokoloff, Taylor & Zafman LLP
Le Thong
Nelms David
Virage Logic Corporation
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