Method and apparatus of reloading erroneous configuration...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S799000

Reexamination Certificate

active

07350134

ABSTRACT:
An improved method and apparatus for reloading frames in which errors are detected during the Programmable Logic Device configuration. A configuration data frame for a FPGA is loaded to the Frame register of the FPGA and also to an error detection circuit which detects errors with the loaded frame. An error counter value is maintained by the apparatus and is incremented each time an error with a frame is detected. The incremented value is compared by a Comparator circuit with a pre-determined threshold value ‘n’. If a match is found then the configuration process is aborted, else the data frame is reloaded in the configuration memory, transferred again to the frame register and rechecked for errors. If no error is detected with the reloaded frame, the error counter value is reset and the next frame is loaded until the FPGA configuration process is over.

REFERENCES:
patent: 5870586 (1999-02-01), Baxter
patent: 6560743 (2003-05-01), Plants
patent: 7111224 (2006-09-01), Trimberger
ALTERA's Application Note 116 “Configuring APEX 20K, FLEX 10K, 6000 Devices,” pp. 1-77, May 2000.
ALTERA's Application Note 33 “Configuring FLEX 8000 devices,” pp. 33-71, Jun. 2000.
Xilinx's Application Note XAPP138 “Virtex FPGA Series Configuration and Readback,” pp. 1-39, Jul. 11, 2002.
Xilinx Inc.,The programmable Logic databook 1999, May 14, 1999, version 1.6, “XC4000E and XC4000X Series Field Programmable Gate Arrays,” pp. 6-49-6-72.

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