Method and apparatus of processing data according to data types

Details Method and apparatus of processing data according to data types Method and apparatus of processing data according to data types

2007-06-05

2007-06-05

Beausoliel, Jr., Robert W. (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S001000, C714S774000, C725S131000, C725S134000, C725S139000, C725S142000, C725S151000

Reexamination Certificate

active

10790782

ABSTRACT:
A method of and apparatus for processing data according to data types. The data processing method is performed by a slave processor and a main processor, wherein the slave processor stores and reads data and the main processor is connected to the slave processor to process the data. The data processing method includes: the main processor, transmitting at least one reference address to the slave processor, analyzing whether transmission data to be communicated to the slave processor is data that has to be processed in real-time or data that does not have to be processed in real-time, setting a relative address of the transmission data according to the analyzed result, and transmitting the relative address to the slave processor, wherein the relative address is an address of the slave processor in which the transmission data to be transmitted to the slave processor is to be stored or an address of the slave processor in which the transmission data to be received from the slave processor is stored, and the slave processor storing the transmitted reference address, determining whether the transmission data is data that has to be processed in real-time or data that does not have to be processed in real-time by comparing the relative address with the reference address, and correcting errors generated when the transmission data is processed, using predetermined processes according to the determined result. Therefore, it is possible to improve error-correction performance, utilize the slave processor for various purposes, and reduce an access time of the main processor.

REFERENCES:
patent: 6400728 (2002-06-01), Ott
patent: 6654901 (2003-11-01), Nakai et al.
patent: 2001/0052130 (2001-12-01), Yap et al.
patent: 2002-90223 (2002-11-01), None

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