Method and apparatus of low power cache operation with a tag hit

Details Method and apparatus of low power cache operation with a tag hit Method and apparatus of low power cache operation with a tag hit

1996-04-22

1998-11-10

Swann, Tod R.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

711118, 711133, 711154, 711205, 39575001, G06F 1200, G06F 1300

Patent

active

058359346

ABSTRACT:
A tag hit enable method for low power cache operation is provided which comprises inactivating all output buffers during all cache operations generating a tag hit enable signal, enabling/disabling dataram output buffers with said tag signal, activating only said output buffers receiving a hit state from a tag ram in order to transfer data from dataram to a CPU data bus, pre-charging said tag hit signals to tag miss signals, and disabling all data output buffers with said tag miss signals.

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