Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1995-06-06
1996-07-23
Nguygen, Tan T.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
36518905, 36523003, 365233, G11C 700
Patent
active
055396968
ABSTRACT:
A synchronous memory device is provided in which a timing and control circuit (28) receives timing and control inputs. A row address buffer (38) and row decoders (40 and 42) operate to enable rows in plural memory sections (30, 32, 34, and 36). Column decoders (58, 60, 62, and 64) operate to enable columns in each of the memory sections (respectively, 32, 36, 30 and 34). The column decoders (58, 60, 62, and 64) decode addresses received from counters (respectively 52, 54, 48, and 50), an adder (46), and a latch (56). Counters (48, 50, 52, and 54) and adder (46) generate column addresses for each memory section based on a starting address, thereby allowing for internal operation at less than the external system frequency. Furthermore, an input buffer (100) is provided that allows data input to the memory device to be received at the system frequency. Once data for each memory section has been received, a substantially simultaneous write operation is performed to each unmasked memory section.
REFERENCES:
patent: 3895360 (1975-07-01), Criccui et al.
patent: 4802132 (1989-01-01), Ohsawa
patent: 4947373 (1990-08-01), Yamaguchi et al.
patent: 5003510 (1991-03-01), Kamisaki
patent: 5016220 (1991-05-01), Yamagata
patent: 5077693 (1991-12-01), Hardee et al.
patent: 5083296 (1992-01-01), Hara et al.
patent: 5126973 (1992-06-01), Gallia et al.
patent: 5136546 (1992-08-01), Fukuda
patent: 5148396 (1992-09-01), Nakada
patent: 5148523 (1992-09-01), Harlin et al.
patent: 5315560 (1994-05-01), Nishimoto et al.
patent: 5384745 (1995-01-01), Konishi et al.
Reese, Ed and Eddy Huang, A Sub-10nS Cache SRAM for High Peformance 32 Bit Microprocessors, IEEE, 1990 Cust. IC confr., pp. 24.2.1-24.2.4.
Wilson, Ron, Will the Search for the Ideal Memory Architecture Ever End?, Computer Design, Jul. 1, 1990, pp. 78-99.
Hochstedler, Charles, Self-Timed SRAMs Pace High-Speed ECL Processors, Semiconductor Memories, 1990, pp. 4-10.
Lineback, J. Robert, System Snags Shouldn't Slow the Boom in Fast Static RAMS, Electronics, Jul. 23, 1987, pp. 60-62.
Triad Semiconductors Inc., Static RAMs have on-chip address and Data Latches for Pipelining, EDN, Dec. 8, 198, p. 116.
Cole, Bernard C., Motorola's Radical SRAM Design Speeds Systems 40%, Electronics, Jul. 23, 1987, pp. 66-68.
Iqbal, Mohammad Shakaib, Internally timed RAMs Build Fast Writable Control Stores, Electronic Design, Aug. 25, 1988, pp. 93-96.
Leibson, Steven, SRAMs' On-Chip Address and data Ltches Boost Throughput in Pipelined Systems, EDN, Oct. 13, 1988, pp. 102-103.
Gallant, John, Special-feature SRAMs, EDN, Jun. 20, 1991, pp. 104-112.
Weber, Samuel, Specialty SRAMs Are Filling the Speed Gap, Electronics, May 1990, pp. 85-87.
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