Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-08-28
2004-06-22
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S207000, C257S202000, C257S203000, C438S017000
Reexamination Certificate
active
06753547
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the fabrication and testing of semiconductor dies before the dies are cut from fabricated wafers.
BACKGROUND OF THE INVENTION
Semiconductor dies are manufactured from wafers by fabricating, testing and dicing of the dies. Dies, also known as “chips”, contain the finished circuitry of semiconductor components, e.g. processors, memory circuits and others. Not all fabricated dies present on a wafer are operable and thus individual dies must be tested and defective dies discarded.
On wafer burn-in testing is one type of test typically used to separate good and bad dies. For the wafer tests, voltage busses Vcc and Vss are often fabricated over a protection passivation layer for the wafer. The protective layer is also selectively etched to expose Vcc and Vss conductive pads on the individual dies which are electrically connected to the Vcc and Vss voltage busses that run across the wafer. This bus and pad structure supplies power to the dies during the wafer burn-in tests. The Vcc and Vss voltage busses can be located in the street area between dies or over the top of dies covered with protective layer.
During wafer level testing, fuses are respectively associated with the dies and are used to isolate a die which is defective and draws excessive current from one or both of the Vcc and Vss busses. In this way, a die drawing excessive current during the on-wafer testing can be disconnected by a blown fuse from the busses and not affect the testing of other dies.
The wafer level testing is typically conducted in a furnace to temperature stress the dies during burn-in testing to check for defects. A series of predetermined voltages may also be applied to the dies during the burn-in test, through the Vcc and Vss busses, in an effort to detect dies which will not operate properly within design specifications under various temperature conditions. The fuses associated with each die are blown automatically when excessive current is drawn or manually when an over-current or latch up condition is detected within a die. (Latchup is a condition where the die circuits lock up and draws damaging levels of high current)
The fuses are important in isolating a defective die from other dies connected to the Vcc and Vss busses during die testing. Typically, sacrificial fuses are provided as part of the sacrificial Vcc and Vss bus structure over the dies or in the street areas between dies. Etching away sacrificial fuses from dies after burn-in complicates post burn-in identification of defective dies. Additional time is required to test each die for high current condition defects rather than a simple continuity check of a die fuse.
Another problem is that existing die processing and testing methods also do not adequately protect non-sacrificial on-die structures during subsequent etching of bonding pads used for electrical connection to the die. Extensive precautions and effort must be undertaken to avoid damaging non-sacrificial components when the sacrificial components are etched away.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus which mitigates problems associated with sacrificial fuses and the undesired etching of non-sacrificial die structures when the sacrificial die test bus structure is removed. In the invention, a first and second sacrificial busses are applied to a wafer and used to supply a first and second voltage (Vcc and Vss) through openings in a passivation layer atop the dies to respective on die Vcc and Vss sacrificial voltage pads. The sacrificial pads are connected to a non-sacrificial standard or secondary on-die voltage pad through a sacrificial metal bus which is only partially etched away when the sacrificial busses are removed thereby providing protection for the non-sacrificial die structures. A fuse is interposed on each die between the standard and secondary voltage pads. A standard voltage pad (e.g. ground or power) is connected to die terminal voltage pins for supplying power and ground voltage (or a first and second voltage) to the die. The fuse will blow when a die draws excessive current during wafer level tests thereby isolating a defective die from the wafer sacrificial voltage busses Vcc and Vss. After burn-in, the sacrificial Vcc and Vss busses, sacrificial die pads and a portion of the on-die sacrificial metal busses are removed from the wafers and the passivation layer is etched to provide an opening to standard and secondary on-die voltage pads of each die. Post burn-in testing and defective die identification can then be accomplished as the sacrificial on-die fuses can continue to be used to isolate dies and identify defective dies by a fuse being blown, after the sacrificial etching. In addition, the on-die voltage pads, which are protected during the sacrificial etching, continue to be available for test probing and conductor bonding.
REFERENCES:
patent: 5391892 (1995-02-01), Devereaux et al.
patent: 5923047 (1999-07-01), Chia et al.
patent: 6091079 (2000-07-01), Green et al.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Jackson Jerome
Micro)n Technology, Inc.
Nguyen Joseph
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