Method and apparatus for variable delay data transfer

Details Method and apparatus for variable delay data transfer Method and apparatus for variable delay data transfer

2004-08-19

2009-10-06

Lee, Thomas (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Reexamination Certificate

active

07600143

ABSTRACT:
A method and apparatus allows data to traverse a cache interface device in one of four transfer modes. A fast bypass mode provides received cache data within the same master clock cycle as it was received, whereas a slow bypass mode provides received cache data within the subsequent master clock cycle. A queue mode provides a programmable amount of delay to be used by the cache interface device, whereby consecutive queue mode provides a First In First Out (FIFO) operation to consecutively retrieve queued data. A block queue mode, on the other hand, provides a method to retrieve queued data using a programmable offset so as to enable partial cache line retrieval without the need to use No Operation (NoP) clock cycles on the cache interface data bus.

REFERENCES:
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patent: 6167528 (2000-12-01), Arcoleo
patent: 6418176 (2002-07-01), Ho et al.
patent: 6486721 (2002-11-01), Greenstreet et al.
patent: 6735732 (2004-05-01), Yamada

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