Method and apparatus for time domain equalization

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

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C713S400000, C327S250000, C327S261000

Reexamination Certificate

active

07020792

ABSTRACT:
A method and apparatus is described that may be utilized to equalize modal velocity changes on a data bus. Modal velocity changes may be equalized by use of variable delays that may be used to equalize modal velocity changes.

REFERENCES:
patent: 4890022 (1989-12-01), Endo
patent: 5471165 (1995-11-01), Liedberg
patent: 5544175 (1996-08-01), Posse
patent: 5872959 (1999-02-01), Nguyen et al.

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