Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-06-17
2008-06-17
Lin, Sun J. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07389484
ABSTRACT:
A process and apparatus are provided for tiling objects, such as design memories, in one or more respective object locations in a layout pattern. For each object, the following steps are performed recursively based on a comparison of at least one of a capacity and a width of the object and that of the respective object location: (1) do nothing; (2) reconfigure the object to have a different capacity and/or width; and (3) split the object into two or more separate objects. The recursion is repeated for each reconfigured object and each separated object.
REFERENCES:
patent: 6553552 (2003-04-01), Khan et al.
patent: 6735754 (2004-05-01), Mehrotra et al.
patent: 6738953 (2004-05-01), Sabharwal et al.
patent: 6775200 (2004-08-01), Khan et al.
patent: 2003/0076534 (2003-04-01), Li et al.
Andreev Alexandre
Neznanov Ilya V.
Nikitin Andrey
Scepanovic Ranko
Lin Sun J.
LSI Corporation
Westman Champlin & Kelly
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