Method and apparatus for the inspection of patterns

Optics: measuring and testing – By configuration comparison – With comparison to master – desired shape – or reference voltage

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356237, G01B 1100, G01N 2100

Patent

active

051737191

ABSTRACT:
The present invention relates to a technique, in the inspection of a defect of a semiconductor memory or the like, in which chip comparison is separated from repetitive pattern comparison in a region of a wafer to be inspected whereby both the comparisons are rendered possible to perform in parallel in one and the same scanning.

REFERENCES:
patent: 4547895 (1985-10-01), Mita et al.
patent: 4603974 (1986-08-01), Matsui

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