Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
1999-09-07
2001-02-27
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S117000
Reexamination Certificate
active
06195616
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electronic circuits and more specifically the functional verification of digital electronic systems.
2. Description of the Relevant Art
An electronic circuit may fail to function correctly due to design errors, fabrication errors, fabrication defects, and/or physical failures. A failure to properly implement a functional specification represents a design error. Fabrication errors are attributable to human error, and include the use of incorrect components, the incorrect installation of components, and incorrect wiring. Examples of fabrication defects, which result from imperfect manufacturing processes, include conductor opens and shorts, mask alignment errors, and improper doping profiles. Physical failures occur due to wear-out and/or environmental factors. The thinning and/or breakage of fine aluminum lead wires inside integrated circuit packages due to electromigration or corrosion are examples of physical failures.
Functional verification (i.e., functional testing) is often performed to validate the correct operation of a system with respect to a set of functional specifications. Functional verification includes applying known stimuli to inputs of a system under test, recording the responses, and comparing the responses to expected responses derived from the set of functional specifications. Any deviation of recorded responses from expected responses represents a failure of a functional test.
The functional testing of a complex digital electronic system is a difficult process requiring large amounts of time and effort. Complex digital electronic systems typically contain memory elements, and have outputs which depend on past inputs as well as current inputs. Such digital electronic systems are called sequential systems, and their status at any given time is referred to as a system state. A digital electronic system with 2
M
possible system states and 2
N
possible input combinations would require the application of all 2
M+N
possible functional tests to completely verify the correct operation of the system. Such a system has a verification space defined by all 2
M+N
possible functional tests. As the number of possible system states and input combinations increases, it quickly becomes impractical to apply all of the 2
M+N
possible tests required to completely verify the correct operation of a complex digital electronic system.
While there is no quantitative measure of how much of the total functional specification is verified by a set of functional tests which does not include all possible tests, confidence that a system functions correctly generally increases with the number of unique functional tests performed and passed which span all areas of the system verification space and exercise all parts of the system implementation.
Functional tests are typically derived manually by persons familiar with the system, however, and the manual generation of large numbers of functional tests for complex systems is a difficult, tedious, time consuming, and error prone process. It would thus be advantageous to provide an method and apparatus for the functional verification of digital electronic systems capable of generating and executing large numbers of functional tests for complex systems at low cost.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a method and apparatus for the functional verification of digital electronic systems in accordance with the present invention. Algorithmic generation of functional tests is employed in order to make the generation of large numbers of functional tests for complex systems practical. A decision tree is created from a functional specification and represents a verification space. Such a decision tree includes an initial goal node, a leaf goal node, and at least one intermediate goal node interconnected by a plurality of directed decision arcs formed between the initial goal node and the leaf goal node. Goal plans assigned to goal nodes include operations which generate functional tests. Functional tests are generated by recursively “walking” the decision tree, the choices of which goal node to visit next being made at random and according to decision weights assigned to each goal node. The decision weights assigned to each goal node in the decision tree may be adjusted to ensure all portions of the verification space are adequately tested.
The apparatus for the functional verification of digital electronic systems includes a test generator, a testing system, a golden unit, and a device under test. The test generator uses a decision tree representation of a verification space to generate functional tests as described above. The test generator provides these functional tests to the testing system as output. The testing system issues functional tests to both the golden device and the device under test. The golden device produces expected responses as output to the testing system. The device under test also produces responses as output to the testing system. The testing system compares expected responses from the golden unit to responses from device under test and produces functional test results. These functional test results flag differences in the responses from the device under test and expected responses from the golden unit as potential functional errors. The functional test results may then be screened by testing personnel to determine if differences in the responses from the device under test and expected responses from golden unit represent functional errors.
The present invention also contemplates the use of specialized structures called monitors to ensure sets of functional tests (i.e., functional test suites) exercise all parts of a system implementation. A device may be implemented in hardware or in any combination of hardware, firmware, and software. A monitor structure used to observe a hardware implementation of a device under test is called a hardware monitor. A monitor structure used to observe an implementation of a device under test which resides in software running in a hardware environment (i.e., a software implementation) is referred to as a software monitor.
Monitors also have a beneficial side effect in that they may also help to discover areas of a verification space unintentionally omitted from a decision tree representation of that verification space. An investigation based on a report from a monitor indicating that one or more functional areas of a system implementation were not fully exercised may reveal that one or more areas of a verification space were omitted from the decision tree representation.
Employing automated functional test generation and test execution, the method and apparatus of the present invention is capable of generating and executing large numbers of functional tests for complex systems at low cost.
REFERENCES:
patent: 4601032 (1986-07-01), Robinson
patent: 4716564 (1987-12-01), Hung et al
patent: 5130936 (1992-07-01), Sheppard et al.
patent: 5469075 (1995-11-01), Oke et al.
patent: 5583786 (1996-12-01), Needham
patent: 5617430 (1997-04-01), Angelotti et al.
patent: 5677915 (1997-10-01), Whetsel
patent: 5684946 (1997-11-01), Ellis et al.
patent: 6101457 (2000-08-01), Barch et al.
Hamid Adnan A.
Reed David F.
Advanced Micro Devices , Inc.
Conley Rose & Tayon
Daffer Kevin L.
Hoff Marc S.
Miller Craig Steven
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