Method and apparatus for testing semiconductor memory device...

Details Method and apparatus for testing semiconductor memory device... Method and apparatus for testing semiconductor memory device...

2004-12-08

2008-12-09

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

07464309

ABSTRACT:
A test method and apparatus for a semiconductor memory device is characterized by the sequentially programmed use of two test different modes. A first test mode tests at least signal line integrity for the semiconductor memory device by testing a merged set of bits line. The second test mode further tests at least signal line integrity after first separating the merged bits lines. Logical combination of test data derived from the first and second test modes are used to generate error detection signals. At least one bit line associated with a parity bit is preferable merged and separated in the foregoing approach.

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patent: 2003/0115518 (2003-06-01), Kleveland et al.
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patent: 2003085996 (2003-03-01), None
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“Isolation merged bit line cell (IMBC) for 1 Gb DRAM and beyond” by PArk et al. This paper appears in: Electron Devices Meeting, 1995., International Publication Date: Dec. 10-13, 1995 On pp. 911-914 ISBN: 0-7803-2700-4 INSPEC Accession No. 5241840.

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