Static information storage and retrieval – Read/write circuit – Testing
Patent
1996-12-31
1998-09-22
Zarabian, A.
Static information storage and retrieval
Read/write circuit
Testing
36523005, G11C 700
Patent
active
058124691
ABSTRACT:
A method of and apparatus for testing multi-port memory performs a shadow read to an adjacent memory cell concurrent with a write operation associated with typical read-write testing. In the presence of a bit wire short or a word wire short, the concurrent read of an adjacent memory cell will cause the value of that cell to be corrupted. The corrupted value is then found by the read-write testing. Consequently, the testing takes no longer than read-write testing. In addition, the testing scheme can be modified for memory with read only ports. An embodiment of the apparatus employs an exclusive OR gate on the least significant bit of the test row address line to generate the shadow read address.
REFERENCES:
patent: 5566371 (1996-10-01), Ogawa
patent: 5579322 (1996-11-01), Orodera
patent: 5590087 (1996-12-01), Chung
Ad J. van de Goor et al., "Fault Models and Tests for Ring Address Type FIFOs", VLSI Test Symposium (IEEE) Jun., 1994, pp. 300-305.
T. Matsumura, "An Efficient Test Method for Embedded Multi-port RAM with BIST Circuitry", International Test Conference 1995, pp. 62-67.
B. Nadeau-Dostie et al., "Serial Interfacting for Embedded-Memory Testing", IEEE Design & Test of Computers, Apr. 1990, pp. 52-63.
Cote Jean-Francois
Nadeau-Dostie Benoit
Klivans Norman R.
Logic Vision, Inc.
Zarabian A.
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